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hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
At present the SiFive PLIC model "priority-base" expects interrupt priority register base starting from source 1 instead source 0, that's why on most platforms "priority-base" is set to 0x04 except 'opentitan' machine. 'opentitan' should have set "priority-base" to 0x04 too. Note the irq number calculation in sifive_plic_{read,write} is correct as the codes make up for the irq number by adding 1. Let's simply update "priority-base" to start from interrupt source 0 and add a comment to make it crystal clear. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-Id: <20221211030829.802437-14-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -140,7 +140,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
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SiFivePLICState *plic = opaque;
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if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
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uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
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uint32_t irq = (addr - plic->priority_base) >> 2;
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return plic->source_priority[irq];
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} else if (addr_between(addr, plic->pending_base, plic->num_sources >> 3)) {
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@ -187,7 +187,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
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SiFivePLICState *plic = opaque;
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if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
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uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
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uint32_t irq = (addr - plic->priority_base) >> 2;
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if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
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/*
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@ -428,6 +428,7 @@ static Property sifive_plic_properties[] = {
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/* number of interrupt sources including interrupt source 0 */
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DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
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DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
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/* interrupt priority register base starting from source 0 */
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DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
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DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
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DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
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@ -155,7 +155,7 @@ enum {
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#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187
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#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
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#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
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#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x00
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#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
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#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
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#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
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@ -65,7 +65,7 @@ enum {
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#define SHAKTI_C_PLIC_NUM_SOURCES 28
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/* Excluding Priority 0 */
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#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
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#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
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#define SHAKTI_C_PLIC_PRIORITY_BASE 0x00
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#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
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#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
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#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
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@ -89,7 +89,7 @@ enum {
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*/
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#define SIFIVE_E_PLIC_NUM_SOURCES 53
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#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
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#define SIFIVE_E_PLIC_PRIORITY_BASE 0x00
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#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
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#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
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#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
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@ -158,7 +158,7 @@ enum {
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#define SIFIVE_U_PLIC_NUM_SOURCES 54
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
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#define SIFIVE_U_PLIC_PRIORITY_BASE 0x00
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#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
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#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
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#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
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@ -98,7 +98,7 @@ enum {
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#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
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#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
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#define VIRT_PLIC_PRIORITY_BASE 0x04
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#define VIRT_PLIC_PRIORITY_BASE 0x00
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#define VIRT_PLIC_PENDING_BASE 0x1000
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#define VIRT_PLIC_ENABLE_BASE 0x2000
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#define VIRT_PLIC_ENABLE_STRIDE 0x80
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