From 5d874e5da23846c40dcb6d73a4c47bb95ff54372 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 24 May 2024 16:20:20 -0700 Subject: [PATCH] target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16) All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode. Fixes a RISU miscompare for invalid insn 0x5ef0c87a. Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in simd_scalar_pairwise") Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240524232121.284515-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5455ae3685..0bdddb8517 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8006,7 +8006,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) case 0x2f: /* FMINP */ /* FP op, size[0] is 32 or 64 bit*/ if (!u) { - if (!dc_isar_feature(aa64_fp16, s)) { + if ((size & 1) || !dc_isar_feature(aa64_fp16, s)) { unallocated_encoding(s); return; } else {