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target/riscv: rvv-1.0: floating-point scalar move instructions 

NaN-boxed the scalar floating-point register based on RVV 1.0's rules.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-39-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:24 +08:00 committed by Alistair Francis
parent c4b3e46f00
commit 5c4eb8fb56
3 changed files with 21 additions and 26 deletions
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4
target/riscv/insn32.decode
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@ -637,8 +637,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm

38
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -3047,14 +3047,19 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* Floating-Point Scalar Move Instructions */
static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
{
if (!s->vill && has_ext(s, RVF) &&
(s->mstatus_fs != 0) && (s->sew != 0)) {
unsigned int len = 8 << s->sew;
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
unsigned int ofs = (8 << s->sew);
unsigned int len = 64 - ofs;
TCGv_i64 t_nan;
vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
if (len < 64) {
tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
MAKE_64BIT_MASK(len, 64 - len));
/* NaN-box f[rd] as necessary for SEW */
if (len) {
t_nan = tcg_constant_i64(UINT64_MAX);
tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
t_nan, ofs, len);
}
mark_fs_dirty(s);
@ -3066,25 +3071,20 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
{
if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
TCGv_i64 t1;
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
/* The instructions ignore LMUL and vector register group. */
uint32_t vlmax = s->vlen >> 3;
TCGv_i64 t1;
TCGLabel *over = gen_new_label();
/* if vl == 0, skip vector register write back */
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
/* zeroed all elements */
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
/* NaN-box f[rs1] as necessary for SEW */
/* NaN-box f[rs1] */
t1 = tcg_temp_new_i64();
if (s->sew == MO_64 && !has_ext(s, RVD)) {
tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
} else {
tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
}
do_nanbox(s, t1, cpu_fpr[a->rs1]);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
mark_vs_dirty(s);

5
target/riscv/internals.h
View File

@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1);
target_ulong fclass_s(uint64_t frs1);
target_ulong fclass_d(uint64_t frs1);
#define SEW8 0
#define SEW16 1
#define SEW32 2
#define SEW64 3
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_riscv_cpu;
#endif