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ppc: Turn a bunch of booleans from int to bool 

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Benjamin Herrenschmidt 2016-06-21 23:48:53 +02:00 committed by David Gibson
parent b781537560
commit 5c3ae92910
1 changed files with 18 additions and 19 deletions
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37
target-ppc/translate.c
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@ -193,22 +193,21 @@ struct DisasContext {
uint32_t opcode; uint32_t opcode;
uint32_t exception; uint32_t exception;
/* Routine used to access memory */ /* Routine used to access memory */
bool pr, hv, dr; bool pr, hv, dr, le_mode;
bool lazy_tlb_flush; bool lazy_tlb_flush;
int mem_idx; int mem_idx;
int access_type; int access_type;
/* Translation flags */ /* Translation flags */
int le_mode;
TCGMemOp default_tcg_memop_mask; TCGMemOp default_tcg_memop_mask;
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
int sf_mode; bool sf_mode;
int has_cfar; bool has_cfar;
#endif #endif
int fpu_enabled; bool fpu_enabled;
int altivec_enabled; bool altivec_enabled;
int vsx_enabled; bool vsx_enabled;
int spe_enabled; bool spe_enabled;
int tm_enabled; bool tm_enabled;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled; int singlestep_enabled;
uint64_t insns_flags; uint64_t insns_flags;
@ -11496,7 +11495,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.insns_flags = env->insns_flags; ctx.insns_flags = env->insns_flags;
ctx.insns_flags2 = env->insns_flags2; ctx.insns_flags2 = env->insns_flags2;
ctx.access_type = -1; ctx.access_type = -1;
ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
ctx.sf_mode = msr_is_64bit(env, env->msr); ctx.sf_mode = msr_is_64bit(env, env->msr);
@ -11507,25 +11506,25 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
(env->mmu_model & POWERPC_MMU_64B)) (env->mmu_model & POWERPC_MMU_64B))
ctx.lazy_tlb_flush = true; ctx.lazy_tlb_flush = true;
ctx.fpu_enabled = msr_fp; ctx.fpu_enabled = !!msr_fp;
if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
ctx.spe_enabled = msr_spe; ctx.spe_enabled = !!msr_spe;
else else
ctx.spe_enabled = 0; ctx.spe_enabled = false;
if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
ctx.altivec_enabled = msr_vr; ctx.altivec_enabled = !!msr_vr;
else else
ctx.altivec_enabled = 0; ctx.altivec_enabled = false;
if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
ctx.vsx_enabled = msr_vsx; ctx.vsx_enabled = !!msr_vsx;
} else { } else {
ctx.vsx_enabled = 0; ctx.vsx_enabled = false;
} }
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
ctx.tm_enabled = msr_tm; ctx.tm_enabled = !!msr_tm;
} else { } else {
ctx.tm_enabled = 0; ctx.tm_enabled = false;
} }
#endif #endif
if ((env->flags & POWERPC_FLAG_SE) && msr_se) if ((env->flags & POWERPC_FLAG_SE) && msr_se)