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hw/arm/exynos4210: Put a9mpcore device into state struct 

The exynos4210 SoC mostly creates its child devices as if it were
board code.  This includes the a9mpcore object.  Switch that to a
new-style "embedded in the state struct" creation, because in the
next commit we're going to want to refer to the object again further
down in the exynos4210_realize() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-04-04 16:46:43 +01:00
parent 019eafddd0
commit 5b2417288e
2 changed files with 8 additions and 5 deletions
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11
hw/arm/exynos4210.c
View File

@ -244,17 +244,16 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
} }
/* Private memory region and Internal GIC */ /* Private memory region and Internal GIC */
dev = qdev_new(TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); busdev = SYS_BUS_DEVICE(&s->a9mpcore);
busdev = SYS_BUS_DEVICE(dev); sysbus_realize(busdev, &error_fatal);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n = 0; n < EXYNOS4210_NCPUS; n++) { for (n = 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n, sysbus_connect_irq(busdev, n,
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0)); qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
} }
for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n); s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
} }
/* Cache controller */ /* Cache controller */
@ -489,6 +488,8 @@ static void exynos4210_init(Object *obj)
g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i); g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ); object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
} }
object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
} }
static void exynos4210_class_init(ObjectClass *klass, void *data) static void exynos4210_class_init(ObjectClass *klass, void *data)

2
include/hw/arm/exynos4210.h
View File

@ -26,6 +26,7 @@
#include "hw/or-irq.h" #include "hw/or-irq.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "hw/cpu/a9mpcore.h"
#include "target/arm/cpu-qom.h" #include "target/arm/cpu-qom.h"
#include "qom/object.h" #include "qom/object.h"
@ -103,6 +104,7 @@ struct Exynos4210State {
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
A9MPPrivState a9mpcore;
}; };
#define TYPE_EXYNOS4210_SOC "exynos4210" #define TYPE_EXYNOS4210_SOC "exynos4210"