mirror of https://github.com/xemu-project/xemu.git
hw/arm/exynos4210: Put a9mpcore device into state struct
The exynos4210 SoC mostly creates its child devices as if it were board code. This includes the a9mpcore object. Switch that to a new-style "embedded in the state struct" creation, because in the next commit we're going to want to refer to the object again further down in the exynos4210_realize() function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
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@ -244,17 +244,16 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
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}
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/* Private memory region and Internal GIC */
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dev = qdev_new(TYPE_A9MPCORE_PRIV);
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qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(busdev, &error_fatal);
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qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
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busdev = SYS_BUS_DEVICE(&s->a9mpcore);
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sysbus_realize(busdev, &error_fatal);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
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for (n = 0; n < EXYNOS4210_NCPUS; n++) {
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sysbus_connect_irq(busdev, n,
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qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
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}
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for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
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s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
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s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
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}
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/* Cache controller */
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@ -489,6 +488,8 @@ static void exynos4210_init(Object *obj)
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g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
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object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
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}
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object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
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}
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static void exynos4210_class_init(ObjectClass *klass, void *data)
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@ -26,6 +26,7 @@
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#include "hw/or-irq.h"
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#include "hw/sysbus.h"
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#include "hw/cpu/a9mpcore.h"
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#include "target/arm/cpu-qom.h"
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#include "qom/object.h"
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@ -103,6 +104,7 @@ struct Exynos4210State {
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I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
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qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
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qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
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A9MPPrivState a9mpcore;
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};
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#define TYPE_EXYNOS4210_SOC "exynos4210"
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