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hw/rtc/mc146818rtc: QOM'ify io_base offset 

Exposing the io_base offset as a QOM property not only allows it to be
configurable but also to be displayed in HMP:

Before:

(qemu) info qtree
       ...
          dev: mc146818rtc, id ""
            gpio-out "" 1
            base_year = 0 (0x0)
            irq = 8 (0x8)
            lost_tick_policy = "discard"

After:

          dev: mc146818rtc, id ""
            gpio-out "" 1
            base_year = 0 (0x0)
            iobase = 112 (0x70)
            irq = 8 (0x8)
            lost_tick_policy = "discard"

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220529184006.10712-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Bernhard Beschow 2022-05-29 20:40:06 +02:00 committed by Philippe Mathieu-Daudé
parent 8f3428cc85
commit 5b21b331be
3 changed files with 8 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/i386/microvm-dt.c
View File

@ -210,7 +210,7 @@ static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev)
{
const char compat[] = "motorola,mc146818";
uint32_t irq = object_property_get_uint(OBJECT(dev), "irq", &error_fatal);
hwaddr base = RTC_ISA_BASE;
hwaddr base = object_property_get_uint(OBJECT(dev), "iobase", &error_fatal);
hwaddr size = 8;
char *nodename;

9
hw/rtc/mc146818rtc.c
View File

@ -74,6 +74,8 @@
#define RTC_CLOCK_RATE 32768
#define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768)
#define RTC_ISA_BASE 0x70
static void rtc_set_time(RTCState *s);
static void rtc_update_time(RTCState *s);
static void rtc_set_cmos(RTCState *s, const struct tm *tm);
@ -941,7 +943,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
qemu_register_suspend_notifier(&s->suspend_notifier);
memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
isa_register_ioport(isadev, &s->io, RTC_ISA_BASE);
isa_register_ioport(isadev, &s->io, s->io_base);
/* register rtc 0x70 port for coalesced_pio */
memory_region_set_flush_coalesced(&s->io);
@ -950,7 +952,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->io, 0, &s->coalesced_io);
memory_region_add_coalescing(&s->coalesced_io, 0, 1);
qdev_set_legacy_instance_id(dev, RTC_ISA_BASE, 3);
qdev_set_legacy_instance_id(dev, s->io_base, 3);
object_property_add_tm(OBJECT(s), "date", rtc_get_date);
@ -983,6 +985,7 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
static Property mc146818rtc_properties[] = {
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
DEFINE_PROP_UINT16("iobase", RTCState, io_base, RTC_ISA_BASE),
DEFINE_PROP_UINT8("irq", RTCState, isairq, RTC_ISA_IRQ),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
lost_tick_policy, LOST_TICK_POLICY_DISCARD),
@ -1028,7 +1031,7 @@ static void rtc_build_aml(AcpiDevAmlIf *adev, Aml *scope)
* does, even though qemu only responds to the first two ports.
*/
crs = aml_resource_template();
aml_append(crs, aml_io(AML_DECODE16, RTC_ISA_BASE, RTC_ISA_BASE,
aml_append(crs, aml_io(AML_DECODE16, s->io_base, s->io_base,
0x01, 0x08));
aml_append(crs, aml_irq_no_flags(s->isairq));

2
include/hw/rtc/mc146818rtc.h
View File

@ -26,6 +26,7 @@ struct RTCState {
uint8_t cmos_data[128];
uint8_t cmos_index;
uint8_t isairq;
uint16_t io_base;
int32_t base_year;
uint64_t base_rtc;
uint64_t last_update;
@ -49,7 +50,6 @@ struct RTCState {
};
#define RTC_ISA_IRQ 8
#define RTC_ISA_BASE 0x70
ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq);