mirror of https://github.com/xemu-project/xemu.git
target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()
All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_validate_set_extensions() helper and always execute it regardless of what the board set in env->misa_ext. This will put more responsibility in how each board is going to init their attributes and extensions if they're not using the defaults. It'll also allow realize() to do its job looking only at the extensions enabled per se, not corner cases that some CPUs might have, and we won't have to change multiple code paths to fix or change how extensions work. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com> [ Changes by AF: - Rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza
Alistair Francis
parent
c66ffcd535
commit
5ab1095213
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@ -625,103 +625,13 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
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}
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}
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static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(dev);
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CPURISCVState *env = &cpu->env;
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
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CPUClass *cc = CPU_CLASS(mcc);
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int i, priv_version = -1;
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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if (cpu->cfg.priv_spec) {
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if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
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priv_version = PRIV_VERSION_1_12_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
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priv_version = PRIV_VERSION_1_11_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
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priv_version = PRIV_VERSION_1_10_0;
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} else {
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error_setg(errp,
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"Unsupported privilege spec version '%s'",
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cpu->cfg.priv_spec);
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return;
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}
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}
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if (priv_version >= PRIV_VERSION_1_10_0) {
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set_priv_version(env, priv_version);
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}
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/* Force disable extensions if priv spec version does not match */
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for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
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if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
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(env->priv_ver < isa_edata_arr[i].min_version)) {
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isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
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#ifndef CONFIG_USER_ONLY
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warn_report("disabling %s extension for hart 0x%lx because "
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"privilege spec version does not match",
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isa_edata_arr[i].name, (unsigned long)env->mhartid);
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#else
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warn_report("disabling %s extension because "
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"privilege spec version does not match",
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isa_edata_arr[i].name);
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#endif
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}
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}
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if (cpu->cfg.mmu) {
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riscv_set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.pmp) {
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riscv_set_feature(env, RISCV_FEATURE_PMP);
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/*
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* Enhanced PMP should only be available
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* on harts with PMP support
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/*
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* Check consistency between chosen extensions while setting
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* cpu->cfg accordingly, doing a set_misa() in the end.
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*/
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if (cpu->cfg.epmp) {
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riscv_set_feature(env, RISCV_FEATURE_EPMP);
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}
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}
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if (cpu->cfg.debug) {
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riscv_set_feature(env, RISCV_FEATURE_DEBUG);
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}
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#ifndef CONFIG_USER_ONLY
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if (cpu->cfg.ext_sstc) {
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riscv_timer_init(cpu);
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}
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#endif /* CONFIG_USER_ONLY */
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/* Validate that MISA_MXL is set properly. */
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switch (env->misa_mxl_max) {
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#ifdef TARGET_RISCV64
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case MXL_RV64:
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case MXL_RV128:
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cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
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break;
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#endif
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case MXL_RV32:
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cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
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break;
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default:
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g_assert_not_reached();
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}
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assert(env->misa_mxl_max == env->misa_mxl);
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/* If only MISA_EXT is unset for misa, then set it from properties */
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if (env->misa_ext == 0) {
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static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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{
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CPURISCVState *env = &cpu->env;
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uint32_t ext = 0;
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/* Do some ISA extension error checking */
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@ -914,6 +824,107 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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}
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set_misa(env, env->misa_mxl, ext);
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}
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static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(dev);
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CPURISCVState *env = &cpu->env;
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
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CPUClass *cc = CPU_CLASS(mcc);
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int i, priv_version = -1;
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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if (cpu->cfg.priv_spec) {
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if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
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priv_version = PRIV_VERSION_1_12_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
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priv_version = PRIV_VERSION_1_11_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
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priv_version = PRIV_VERSION_1_10_0;
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} else {
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error_setg(errp,
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"Unsupported privilege spec version '%s'",
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cpu->cfg.priv_spec);
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return;
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}
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}
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if (priv_version >= PRIV_VERSION_1_10_0) {
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set_priv_version(env, priv_version);
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}
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/* Force disable extensions if priv spec version does not match */
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for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
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if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
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(env->priv_ver < isa_edata_arr[i].min_version)) {
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isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
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#ifndef CONFIG_USER_ONLY
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warn_report("disabling %s extension for hart 0x%lx because "
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"privilege spec version does not match",
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isa_edata_arr[i].name, (unsigned long)env->mhartid);
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#else
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warn_report("disabling %s extension because "
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"privilege spec version does not match",
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isa_edata_arr[i].name);
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#endif
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}
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}
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if (cpu->cfg.mmu) {
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riscv_set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.pmp) {
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riscv_set_feature(env, RISCV_FEATURE_PMP);
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/*
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* Enhanced PMP should only be available
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* on harts with PMP support
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*/
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if (cpu->cfg.epmp) {
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riscv_set_feature(env, RISCV_FEATURE_EPMP);
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}
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}
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if (cpu->cfg.debug) {
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riscv_set_feature(env, RISCV_FEATURE_DEBUG);
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}
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#ifndef CONFIG_USER_ONLY
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if (cpu->cfg.ext_sstc) {
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riscv_timer_init(cpu);
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}
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#endif /* CONFIG_USER_ONLY */
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/* Validate that MISA_MXL is set properly. */
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switch (env->misa_mxl_max) {
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#ifdef TARGET_RISCV64
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case MXL_RV64:
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case MXL_RV128:
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cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
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break;
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#endif
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case MXL_RV32:
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cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
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break;
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default:
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g_assert_not_reached();
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}
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assert(env->misa_mxl_max == env->misa_mxl);
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riscv_cpu_validate_set_extensions(cpu, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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#ifndef CONFIG_USER_ONLY
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