mirror of https://github.com/xemu-project/xemu.git
SMP support - cpu_single_env usage fix - a20 helpers - dynamic Multi Processor BIOS table generation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1645 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
c68ea7043f
commit
59b8ad81c4
199
hw/pc.c
199
hw/pc.c
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@ -86,10 +86,11 @@ int cpu_get_pic_interrupt(CPUState *env)
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static void pic_irq_request(void *opaque, int level)
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{
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CPUState *env = opaque;
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if (level)
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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else
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cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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/* PC cmos mappings */
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@ -287,15 +288,26 @@ static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
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(dummy_refresh_clock << 4);
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}
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void ioport_set_a20(int enable)
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{
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/* XXX: send to all CPUs ? */
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cpu_x86_set_a20(first_cpu, enable);
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}
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int ioport_get_a20(void)
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{
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return ((first_cpu->a20_mask >> 20) & 1);
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}
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static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
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{
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cpu_x86_set_a20(cpu_single_env, (val >> 1) & 1);
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ioport_set_a20((val >> 1) & 1);
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/* XXX: bit 0 is fast reset */
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}
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static uint32_t ioport92_read(void *opaque, uint32_t addr)
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{
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return ((cpu_single_env->a20_mask >> 20) & 1) << 1;
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return ioport_get_a20() << 1;
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}
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/***********************************************************/
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@ -391,6 +403,162 @@ int load_kernel(const char *filename, uint8_t *addr,
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return -1;
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}
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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}
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/*************************************************/
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static void putb(uint8_t **pp, int val)
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{
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uint8_t *q;
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q = *pp;
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*q++ = val;
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*pp = q;
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}
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static void putstr(uint8_t **pp, const char *str)
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{
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uint8_t *q;
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q = *pp;
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while (*str)
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*q++ = *str++;
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*pp = q;
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}
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static void putle16(uint8_t **pp, int val)
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{
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uint8_t *q;
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q = *pp;
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*q++ = val;
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*q++ = val >> 8;
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*pp = q;
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}
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static void putle32(uint8_t **pp, int val)
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{
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uint8_t *q;
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q = *pp;
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*q++ = val;
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*q++ = val >> 8;
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*q++ = val >> 16;
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*q++ = val >> 24;
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*pp = q;
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}
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static int mpf_checksum(const uint8_t *data, int len)
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{
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int sum, i;
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sum = 0;
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for(i = 0; i < len; i++)
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sum += data[i];
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return sum & 0xff;
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}
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/* Build the Multi Processor table in the BIOS. Same values as Bochs. */
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static void bios_add_mptable(uint8_t *bios_data)
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{
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uint8_t *mp_config_table, *q, *float_pointer_struct;
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int ioapic_id, offset, i, len;
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if (smp_cpus <= 1)
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return;
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mp_config_table = bios_data + 0xcc00;
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q = mp_config_table;
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putstr(&q, "PCMP"); /* "PCMP signature */
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putle16(&q, 0); /* table length (patched later) */
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putb(&q, 4); /* spec rev */
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putb(&q, 0); /* checksum (patched later) */
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putstr(&q, "QEMUCPU "); /* OEM id */
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putstr(&q, "0.1 "); /* vendor id */
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putle32(&q, 0); /* OEM table ptr */
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putle16(&q, 0); /* OEM table size */
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putle16(&q, 20); /* entry count */
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putle32(&q, 0xfee00000); /* local APIC addr */
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putle16(&q, 0); /* ext table length */
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putb(&q, 0); /* ext table checksum */
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putb(&q, 0); /* reserved */
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for(i = 0; i < smp_cpus; i++) {
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putb(&q, 0); /* entry type = processor */
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putb(&q, i); /* APIC id */
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putb(&q, 0x11); /* local APIC version number */
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if (i == 0)
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putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
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else
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putb(&q, 1); /* cpu flags: enabled */
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putb(&q, 0); /* cpu signature */
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putb(&q, 6);
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putb(&q, 0);
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putb(&q, 0);
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putle16(&q, 0x201); /* feature flags */
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putle16(&q, 0);
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putle16(&q, 0); /* reserved */
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putle16(&q, 0);
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putle16(&q, 0);
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putle16(&q, 0);
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}
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/* isa bus */
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putb(&q, 1); /* entry type = bus */
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putb(&q, 0); /* bus ID */
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putstr(&q, "ISA ");
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/* ioapic */
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ioapic_id = smp_cpus;
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putb(&q, 2); /* entry type = I/O APIC */
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putb(&q, ioapic_id); /* apic ID */
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putb(&q, 0x11); /* I/O APIC version number */
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putb(&q, 1); /* enable */
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putle32(&q, 0xfec00000); /* I/O APIC addr */
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/* irqs */
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for(i = 0; i < 16; i++) {
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putb(&q, 3); /* entry type = I/O interrupt */
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putb(&q, 0); /* interrupt type = vectored interrupt */
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putb(&q, 0); /* flags: po=0, el=0 */
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putb(&q, 0);
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putb(&q, 0); /* source bus ID = ISA */
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putb(&q, i); /* source bus IRQ */
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putb(&q, ioapic_id); /* dest I/O APIC ID */
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putb(&q, i); /* dest I/O APIC interrupt in */
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}
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/* patch length */
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len = q - mp_config_table;
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mp_config_table[4] = len;
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mp_config_table[5] = len >> 8;
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mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
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/* align to 16 */
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offset = q - bios_data;
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offset = (offset + 15) & ~15;
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float_pointer_struct = bios_data + offset;
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/* floating pointer structure */
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q = float_pointer_struct;
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putstr(&q, "_MP_");
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/* pointer to MP config table */
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putle32(&q, mp_config_table - bios_data + 0x000f0000);
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putb(&q, 1); /* length in 16 byte units */
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putb(&q, 4); /* MP spec revision */
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putb(&q, 0); /* checksum (patched later) */
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putb(&q, 0); /* MP feature byte 1 */
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putb(&q, 0);
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putb(&q, 0);
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putb(&q, 0);
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putb(&q, 0);
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float_pointer_struct[10] =
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-mpf_checksum(float_pointer_struct, q - float_pointer_struct);
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}
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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@ -418,9 +586,26 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
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unsigned long bios_offset, vga_bios_offset;
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int bios_size, isa_bios_size;
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PCIBus *pci_bus;
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CPUState *env;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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for(i = 0; i < smp_cpus; i++) {
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env = cpu_init();
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if (i != 0)
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env->cpu_halted = 1;
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if (smp_cpus > 1) {
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/* XXX: enable it in all cases */
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env->cpuid_features |= CPUID_APIC;
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}
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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if (pci_enabled) {
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apic_init(env);
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}
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}
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, 0);
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@ -441,6 +626,9 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
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fprintf(stderr, "qemu: could not load PC bios '%s'\n", buf);
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exit(1);
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}
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if (bios_size == 65536) {
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bios_add_mptable(phys_ram_base + bios_offset);
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}
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/* VGA BIOS load */
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if (cirrus_vga_enabled) {
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@ -559,10 +747,9 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
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register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
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if (pci_enabled) {
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apic_init(cpu_single_env);
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ioapic = ioapic_init();
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}
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isa_pic = pic_init(pic_irq_request, cpu_single_env);
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isa_pic = pic_init(pic_irq_request, first_cpu);
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pit = pit_init(0x40, 0);
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if (pci_enabled) {
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pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
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