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aspeed queue: 

* support AST2700 network
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Merge tag 'pull-aspeed-20240709' of https://github.com/legoater/qemu into staging

aspeed queue:

* support AST2700 network

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# gpg: Signature made Tue 09 Jul 2024 04:51:03 AM PDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20240709' of https://github.com/legoater/qemu:
  machine_aspeed.py: update to test network for AST2700
  machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for AST2700
  hw/block: m25p80: support quad mode for w25q01jvq
  aspeed/soc: set dma64 property for AST2700 ftgmac100
  hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits
  hw/net:ftgmac100: introduce TX and RX ring base address high registers to support 64 bits
  hw/net:ftgmac100: update ring base address to 64 bits
  hw/net:ftgmac100: update memory region size to 64KB

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-07-09 07:13:55 -07:00
parent 4a3eceb403 d847ea7cfc
commit 59084feb25
5 changed files with 162 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/arm/aspeed_ast27x0.c
View File

@ -552,9 +552,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
return;
}
/* Net */
for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
&error_abort);
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "dma64", true,
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
return;
}

16
hw/block/m25p80.c
View File

@ -416,6 +416,7 @@ typedef enum {
/*
* Micron: 0x35 - enable QPI
* Spansion: 0x35 - read control register
* Winbond: 0x35 - quad enable
*/
RDCR_EQIO = 0x35,
RSTQIO = 0xf5,
@ -798,6 +799,11 @@ static void complete_collecting_data(Flash *s)
s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
}
break;
case MAN_WINBOND:
if (s->len > 1) {
s->quad_enable = !!(s->data[1] & 0x02);
}
break;
default:
break;
}
@ -1254,6 +1260,10 @@ static void decode_new_cmd(Flash *s, uint32_t value)
s->needed_bytes = 2;
s->state = STATE_COLLECTING_VAR_LEN_DATA;
break;
case MAN_WINBOND:
s->needed_bytes = 2;
s->state = STATE_COLLECTING_VAR_LEN_DATA;
break;
default:
s->needed_bytes = 1;
s->state = STATE_COLLECTING_DATA;
@ -1431,6 +1441,12 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case MAN_MACRONIX:
s->quad_enable = true;
break;
case MAN_WINBOND:
s->data[0] = (!!s->quad_enable) << 1;
s->pos = 0;
s->len = 1;
s->state = STATE_READING_DATA;
break;
default:
break;
}

147
hw/net/ftgmac100.c
View File

@ -56,6 +56,16 @@
#define FTGMAC100_PHYDATA 0x64
#define FTGMAC100_FCR 0x68
/*
* FTGMAC100 registers high
*
* values below are offset by - FTGMAC100_REG_HIGH_OFFSET from datasheet
* because its memory region is start at FTGMAC100_REG_HIGH_OFFSET
*/
#define FTGMAC100_NPTXR_BADR_HIGH (0x17C - FTGMAC100_REG_HIGH_OFFSET)
#define FTGMAC100_HPTXR_BADR_HIGH (0x184 - FTGMAC100_REG_HIGH_OFFSET)
#define FTGMAC100_RXR_BADR_HIGH (0x18C - FTGMAC100_REG_HIGH_OFFSET)
/*
* Interrupt status register & interrupt enable register
*/
@ -165,6 +175,8 @@
#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
#define FTGMAC100_TXDES1_TXIC (1 << 31)
#define FTGMAC100_TXDES2_TXBUF_BADR_HI(x) (((x) >> 16) & 0x7)
/*
* Receive descriptor
*/
@ -198,13 +210,15 @@
#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
#define FTGMAC100_RXDES2_RXBUF_BADR_HI(x) (((x) >> 16) & 0x7)
/*
* Receive and transmit Buffer Descriptor
*/
typedef struct {
uint32_t des0;
uint32_t des1;
uint32_t des2; /* not used by HW */
uint32_t des2; /* used by HW 64 bits DMA */
uint32_t des3;
} FTGMAC100Desc;
@ -515,12 +529,13 @@ out:
return frame_size;
}
static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
uint32_t tx_descriptor)
static void ftgmac100_do_tx(FTGMAC100State *s, uint64_t tx_ring,
uint64_t tx_descriptor)
{
int frame_size = 0;
uint8_t *ptr = s->frame;
uint32_t addr = tx_descriptor;
uint64_t addr = tx_descriptor;
uint64_t buf_addr = 0;
uint32_t flags = 0;
while (1) {
@ -559,7 +574,12 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
len = sizeof(s->frame) - frame_size;
}
if (dma_memory_read(&address_space_memory, bd.des3,
buf_addr = bd.des3;
if (s->dma64) {
buf_addr = deposit64(buf_addr, 32, 32,
FTGMAC100_TXDES2_TXBUF_BADR_HI(bd.des2));
}
if (dma_memory_read(&address_space_memory, buf_addr,
ptr, len, MEMTXATTRS_UNSPECIFIED)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
__func__, bd.des3);
@ -726,9 +746,9 @@ static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
case FTGMAC100_MATH1:
return s->math[1];
case FTGMAC100_RXR_BADR:
return s->rx_ring;
return extract64(s->rx_ring, 0, 32);
case FTGMAC100_NPTXR_BADR:
return s->tx_ring;
return extract64(s->tx_ring, 0, 32);
case FTGMAC100_ITC:
return s->itc;
case FTGMAC100_DBLAC:
@ -799,9 +819,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
HWADDR_PRIx "\n", __func__, value);
return;
}
s->rx_ring = value;
s->rx_descriptor = s->rx_ring;
s->rx_ring = deposit64(s->rx_ring, 0, 32, value);
s->rx_descriptor = deposit64(s->rx_descriptor, 0, 32, value);
break;
case FTGMAC100_RBSR: /* DMA buffer size */
@ -814,8 +833,8 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
HWADDR_PRIx "\n", __func__, value);
return;
}
s->tx_ring = value;
s->tx_descriptor = s->tx_ring;
s->tx_ring = deposit64(s->tx_ring, 0, 32, value);
s->tx_descriptor = deposit64(s->tx_descriptor, 0, 32, value);
break;
case FTGMAC100_NPTXPD: /* Trigger transmit */
@ -914,6 +933,60 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
ftgmac100_update_irq(s);
}
static uint64_t ftgmac100_high_read(void *opaque, hwaddr addr, unsigned size)
{
FTGMAC100State *s = FTGMAC100(opaque);
uint64_t val = 0;
switch (addr) {
case FTGMAC100_NPTXR_BADR_HIGH:
val = extract64(s->tx_ring, 32, 32);
break;
case FTGMAC100_HPTXR_BADR_HIGH:
/* High Priority Transmit Ring Base High Address */
qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
case FTGMAC100_RXR_BADR_HIGH:
val = extract64(s->rx_ring, 32, 32);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
}
return val;
}
static void ftgmac100_high_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
FTGMAC100State *s = FTGMAC100(opaque);
switch (addr) {
case FTGMAC100_NPTXR_BADR_HIGH:
s->tx_ring = deposit64(s->tx_ring, 32, 32, value);
s->tx_descriptor = deposit64(s->tx_descriptor, 32, 32, value);
break;
case FTGMAC100_HPTXR_BADR_HIGH:
/* High Priority Transmit Ring Base High Address */
qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
case FTGMAC100_RXR_BADR_HIGH:
s->rx_ring = deposit64(s->rx_ring, 32, 32, value);
s->rx_descriptor = deposit64(s->rx_descriptor, 32, 32, value);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
HWADDR_PRIx "\n", __func__, addr);
break;
}
ftgmac100_update_irq(s);
}
static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
{
unsigned mcast_idx;
@ -957,9 +1030,9 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
FTGMAC100Desc bd;
uint32_t flags = 0;
uint32_t addr;
uint64_t addr;
uint32_t crc;
uint32_t buf_addr;
uint64_t buf_addr = 0;
uint8_t *crc_ptr;
uint32_t buf_len;
size_t size = len;
@ -1024,7 +1097,12 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
if (size < 4) {
buf_len += size - 4;
}
buf_addr = bd.des3;
if (s->dma64) {
buf_addr = deposit64(buf_addr, 32, 32,
FTGMAC100_RXDES2_RXBUF_BADR_HI(bd.des2));
}
if (first && proto == ETH_P_VLAN && buf_len >= 18) {
bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
@ -1078,6 +1156,14 @@ static const MemoryRegionOps ftgmac100_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const MemoryRegionOps ftgmac100_high_ops = {
.read = ftgmac100_high_read,
.write = ftgmac100_high_write,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void ftgmac100_cleanup(NetClientState *nc)
{
FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
@ -1107,9 +1193,23 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
}
memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
TYPE_FTGMAC100, 0x2000);
sysbus_init_mmio(sbd, &s->iomem);
memory_region_init(&s->iomem_container, OBJECT(s),
TYPE_FTGMAC100 ".container", FTGMAC100_MEM_SIZE);
sysbus_init_mmio(sbd, &s->iomem_container);
memory_region_init_io(&s->iomem, OBJECT(s), &ftgmac100_ops, s,
TYPE_FTGMAC100 ".regs", FTGMAC100_REG_MEM_SIZE);
memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
if (s->dma64) {
memory_region_init_io(&s->iomem_high, OBJECT(s), &ftgmac100_high_ops,
s, TYPE_FTGMAC100 ".regs.high",
FTGMAC100_REG_HIGH_MEM_SIZE);
memory_region_add_subregion(&s->iomem_container,
FTGMAC100_REG_HIGH_OFFSET,
&s->iomem_high);
}
sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
@ -1121,18 +1221,14 @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
static const VMStateDescription vmstate_ftgmac100 = {
.name = TYPE_FTGMAC100,
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(irq_state, FTGMAC100State),
VMSTATE_UINT32(isr, FTGMAC100State),
VMSTATE_UINT32(ier, FTGMAC100State),
VMSTATE_UINT32(rx_enabled, FTGMAC100State),
VMSTATE_UINT32(rx_ring, FTGMAC100State),
VMSTATE_UINT32(rbsr, FTGMAC100State),
VMSTATE_UINT32(tx_ring, FTGMAC100State),
VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
VMSTATE_UINT32(itc, FTGMAC100State),
VMSTATE_UINT32(aptcr, FTGMAC100State),
@ -1151,6 +1247,10 @@ static const VMStateDescription vmstate_ftgmac100 = {
VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
VMSTATE_UINT64(rx_ring, FTGMAC100State),
VMSTATE_UINT64(tx_ring, FTGMAC100State),
VMSTATE_UINT64(rx_descriptor, FTGMAC100State),
VMSTATE_UINT64(tx_descriptor, FTGMAC100State),
VMSTATE_END_OF_LIST()
}
};
@ -1158,6 +1258,7 @@ static const VMStateDescription vmstate_ftgmac100 = {
static Property ftgmac100_properties[] = {
DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
DEFINE_PROP_BOOL("dma64", FTGMAC100State, dma64, false),
DEFINE_PROP_END_OF_LIST(),
};

17
include/hw/net/ftgmac100.h
View File

@ -14,6 +14,11 @@
#define TYPE_FTGMAC100 "ftgmac100"
OBJECT_DECLARE_SIMPLE_TYPE(FTGMAC100State, FTGMAC100)
#define FTGMAC100_MEM_SIZE 0x1000
#define FTGMAC100_REG_MEM_SIZE 0x100
#define FTGMAC100_REG_HIGH_MEM_SIZE 0x100
#define FTGMAC100_REG_HIGH_OFFSET 0x100
#include "hw/sysbus.h"
#include "net/net.h"
@ -30,7 +35,9 @@ struct FTGMAC100State {
NICState *nic;
NICConf conf;
qemu_irq irq;
MemoryRegion iomem_container;
MemoryRegion iomem;
MemoryRegion iomem_high;
uint8_t frame[FTGMAC100_MAX_FRAME_SIZE];
@ -38,10 +45,6 @@ struct FTGMAC100State {
uint32_t isr;
uint32_t ier;
uint32_t rx_enabled;
uint32_t rx_ring;
uint32_t rx_descriptor;
uint32_t tx_ring;
uint32_t tx_descriptor;
uint32_t math[2];
uint32_t rbsr;
uint32_t itc;
@ -54,7 +57,10 @@ struct FTGMAC100State {
uint32_t phycr;
uint32_t phydata;
uint32_t fcr;
uint64_t rx_ring;
uint64_t rx_descriptor;
uint64_t tx_ring;
uint64_t tx_descriptor;
uint32_t phy_status;
uint32_t phy_control;
@ -65,6 +71,7 @@ struct FTGMAC100State {
bool aspeed;
uint32_t txdes0_edotr;
uint32_t rxdes0_edorr;
bool dma64;
};
#define TYPE_ASPEED_MII "aspeed-mmi"

12
tests/avocado/machine_aspeed.py
View File

@ -313,14 +313,14 @@ class AST2x00MachineSDK(QemuSystemTest, LinuxSSHMixIn):
def do_test_aarch64_aspeed_sdk_start(self, image):
self.vm.set_console()
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw')
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
'-net', 'nic', '-net', 'user,hostfwd=:127.0.0.1:0-:22')
self.vm.launch()
self.wait_for_console_pattern('U-Boot 2023.10')
self.wait_for_console_pattern('## Loading kernel from FIT Image')
self.wait_for_console_pattern('Starting kernel ...')
self.wait_for_console_pattern("systemd[1]: Hostname set to")
@skipUnless(os.getenv('QEMU_TEST_FLAKY_TESTS'), 'Test is unstable on GitLab')
@ -387,15 +387,15 @@ class AST2x00MachineSDK(QemuSystemTest, LinuxSSHMixIn):
year = time.strftime("%Y")
self.ssh_command_output_contains('/sbin/hwclock -f /dev/rtc1', year);
def test_aarch64_ast2700_evb_sdk_v09_01(self):
def test_aarch64_ast2700_evb_sdk_v09_02(self):
"""
:avocado: tags=arch:aarch64
:avocado: tags=machine:ast2700-evb
"""
image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
'download/v09.01/ast2700-default-obmc.tar.gz')
image_hash = 'b1cc0fd73c7650d34c9c8459a243f52a91e9e27144b8608b2645ab19461d1e07'
'download/v09.02/ast2700-default-obmc.tar.gz')
image_hash = 'ac969c2602f4e6bdb69562ff466b89ae3fe1d86e1f6797bb7969d787f82116a7'
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
archive.extract(image_path, self.workdir)
@ -436,4 +436,6 @@ class AST2x00MachineSDK(QemuSystemTest, LinuxSSHMixIn):
self.vm.add_args('-smp', str(num_cpu))
self.do_test_aarch64_aspeed_sdk_start(image_dir + 'image-bmc')
self.wait_for_console_pattern('nodistro.0 ast2700-default ttyS12')
self.ssh_connect('root', '0penBmc', False)