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target/arm: Simplify disas_arm_insn 

Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-45-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:34 -07:00 committed by Peter Maydell
parent f843e77144
commit 590057d969
1 changed files with 16 additions and 53 deletions
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69
target/arm/translate.c
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@ -10364,7 +10364,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a)
static void disas_arm_insn(DisasContext *s, unsigned int insn) static void disas_arm_insn(DisasContext *s, unsigned int insn)
{ {
unsigned int cond, op1; unsigned int cond = insn >> 28;
/* M variants do not implement ARM mode; this must raise the INVSTATE /* M variants do not implement ARM mode; this must raise the INVSTATE
* UsageFault exception. * UsageFault exception.
@ -10374,7 +10374,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
default_exception_el(s)); default_exception_el(s));
return; return;
} }
cond = insn >> 28;
if (cond == 0xf) { if (cond == 0xf) {
/* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
@ -10439,11 +10438,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
goto illegal_op; goto illegal_op;
} }
return; return;
} else if ((insn & 0x0fe00000) == 0x0c400000) {
/* Coprocessor double register transfer. */
ARCH(5TE);
} else if ((insn & 0x0f000010) == 0x0e000010) {
/* Additional coprocessor register transfer. */
} }
goto illegal_op; goto illegal_op;
} }
@ -10458,55 +10452,24 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
} }
/* fall back to legacy decoder */ /* fall back to legacy decoder */
if ((insn & 0x0f900000) == 0x03000000) { switch ((insn >> 24) & 0xf) {
/* All done in decodetree. Illegal ops reach here. */ case 0xc:
goto illegal_op; case 0xd:
} else if ((insn & 0x0f900000) == 0x01000000 case 0xe:
&& (insn & 0x00000090) != 0x00000090) { if (((insn >> 8) & 0xe) == 10) {
/* miscellaneous instructions */ /* VFP. */
/* All done in decodetree. Illegal ops reach here. */ if (disas_vfp_insn(s, insn)) {
goto illegal_op;
} else if (((insn & 0x0e000000) == 0 &&
(insn & 0x00000090) != 0x90) ||
((insn & 0x0e000000) == (1 << 25))) {
/* Data-processing (reg, reg-shift-reg, imm). */
/* All done in decodetree. Reach here for illegal ops. */
goto illegal_op;
} else {
/* other instructions */
op1 = (insn >> 24) & 0xf;
switch(op1) {
case 0x0:
case 0x1:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
case 0x08:
case 0x09:
case 0xa:
case 0xb:
case 0xf:
/* All done in decodetree. Reach here for illegal ops. */
goto illegal_op;
case 0xc:
case 0xd:
case 0xe:
if (((insn >> 8) & 0xe) == 10) {
/* VFP. */
if (disas_vfp_insn(s, insn)) {
goto illegal_op;
}
} else if (disas_coproc_insn(s, insn)) {
/* Coprocessor. */
goto illegal_op; goto illegal_op;
} }
break; } else if (disas_coproc_insn(s, insn)) {
default: /* Coprocessor. */
illegal_op: goto illegal_op;
unallocated_encoding(s);
break;
} }
break;
default:
illegal_op:
unallocated_encoding(s);
break;
} }
} }