mirror of https://github.com/xemu-project/xemu.git
lm32: add Milkymist Minimac2 support
This patch adds support for Milkymist's minimal Ethernet MAC v2. It superseds minimac1. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Michael Walle
Edgar E. Iglesias
parent
f3172a0e2e
commit
57aa265d46
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@ -271,7 +271,7 @@ obj-lm32-y += lm32_sys.o
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obj-lm32-y += milkymist-ac97.o
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obj-lm32-y += milkymist-hpdmc.o
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obj-lm32-y += milkymist-memcard.o
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obj-lm32-y += milkymist-minimac.o
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obj-lm32-y += milkymist-minimac2.o
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obj-lm32-y += milkymist-pfpu.o
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obj-lm32-y += milkymist-softusb.o
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obj-lm32-y += milkymist-sysctl.o
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@ -1,6 +1,9 @@
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#ifndef QEMU_HW_MILKYMIST_H
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#define QEMU_HW_MILKYMIST_H
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#include "qdev.h"
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#include "qdev-addr.h"
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static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
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qemu_irq rx_irq, qemu_irq tx_irq)
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{
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@ -183,6 +186,23 @@ static inline DeviceState *milkymist_minimac_create(target_phys_addr_t base,
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return dev;
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}
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static inline DeviceState *milkymist_minimac2_create(target_phys_addr_t base,
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target_phys_addr_t buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
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{
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DeviceState *dev;
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qemu_check_nic_model(&nd_table[0], "minimac2");
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dev = qdev_create(NULL, "milkymist-minimac2");
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qdev_prop_set_taddr(dev, "buffers_base", buffers_base);
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qdev_set_nic_properties(dev, &nd_table[0]);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, rx_irq);
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sysbus_connect_irq(sysbus_from_qdev(dev), 1, tx_irq);
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return dev;
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}
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static inline DeviceState *milkymist_softusb_create(target_phys_addr_t base,
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qemu_irq irq, uint32_t pmem_base, uint32_t pmem_size,
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uint32_t dmem_base, uint32_t dmem_size)
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@ -1,7 +1,7 @@
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/*
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* QEMU model of the Milkymist minimac block.
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* QEMU model of the Milkymist minimac2 block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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* Copyright (c) 2011 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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@ -18,7 +18,7 @@
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*
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*
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* Specification available at:
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* http://www.milkymist.org/socdoc/minimac.pdf
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* not available yet
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*
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*/
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@ -27,6 +27,7 @@
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#include "trace.h"
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#include "net.h"
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#include "qemu-error.h"
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#include "qdev-addr.h"
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#include <zlib.h>
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@ -34,25 +35,15 @@ enum {
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R_SETUP = 0,
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R_MDIO,
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R_STATE0,
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R_ADDR0,
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R_COUNT0,
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R_STATE1,
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R_ADDR1,
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R_COUNT1,
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R_STATE2,
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R_ADDR2,
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R_COUNT2,
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R_STATE3,
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R_ADDR3,
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R_COUNT3,
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R_TXADDR,
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R_TXCOUNT,
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R_MAX
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};
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enum {
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SETUP_RX_RST = (1<<0),
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SETUP_TX_RST = (1<<2),
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SETUP_PHY_RST = (1<<0),
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};
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enum {
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@ -85,9 +76,10 @@ enum {
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R_PHY_MAX = 32
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};
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#define MINIMAC_MTU 1530
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#define MINIMAC2_MTU 1530
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#define MINIMAC2_BUFFER_SIZE 2048
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struct MilkymistMinimacMdioState {
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struct MilkymistMinimac2MdioState {
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int last_clk;
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int count;
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uint32_t data;
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@ -97,50 +89,55 @@ struct MilkymistMinimacMdioState {
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uint8_t phy_addr;
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uint8_t reg_addr;
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};
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typedef struct MilkymistMinimacMdioState MilkymistMinimacMdioState;
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typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
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struct MilkymistMinimacState {
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struct MilkymistMinimac2State {
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SysBusDevice busdev;
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NICState *nic;
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NICConf conf;
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char *phy_model;
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target_phys_addr_t buffers_base;
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qemu_irq rx_irq;
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qemu_irq tx_irq;
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uint32_t regs[R_MAX];
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MilkymistMinimacMdioState mdio;
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MilkymistMinimac2MdioState mdio;
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uint16_t phy_regs[R_PHY_MAX];
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uint8_t *rx0_buf;
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uint8_t *rx1_buf;
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uint8_t *tx_buf;
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};
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typedef struct MilkymistMinimacState MilkymistMinimacState;
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typedef struct MilkymistMinimac2State MilkymistMinimac2State;
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static const uint8_t preamble_sfd[] = {
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0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
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};
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static void minimac_mdio_write_reg(MilkymistMinimacState *s,
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static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
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uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
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{
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trace_milkymist_minimac_mdio_write(phy_addr, reg_addr, value);
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trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
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/* nop */
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}
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static uint16_t minimac_mdio_read_reg(MilkymistMinimacState *s,
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static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
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uint8_t phy_addr, uint8_t reg_addr)
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{
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uint16_t r = s->phy_regs[reg_addr];
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trace_milkymist_minimac_mdio_read(phy_addr, reg_addr, r);
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trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
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return r;
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}
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static void minimac_update_mdio(MilkymistMinimacState *s)
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static void minimac2_update_mdio(MilkymistMinimac2State *s)
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{
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MilkymistMinimacMdioState *m = &s->mdio;
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MilkymistMinimac2MdioState *m = &s->mdio;
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/* detect rising clk edge */
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if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
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@ -173,7 +170,7 @@ static void minimac_update_mdio(MilkymistMinimacState *s)
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}
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if (m->state == MDIO_STATE_READING) {
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m->data_out = minimac_mdio_read_reg(s, m->phy_addr,
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m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
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m->reg_addr);
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}
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}
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@ -192,7 +189,7 @@ static void minimac_update_mdio(MilkymistMinimacState *s)
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if (m->count == 0 && m->state) {
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if (m->state == MDIO_STATE_WRITING) {
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uint16_t data = m->data & 0xffff;
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minimac_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
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minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
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}
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m->state = MDIO_STATE_IDLE;
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}
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@ -208,7 +205,7 @@ static size_t assemble_frame(uint8_t *buf, size_t size,
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uint32_t crc;
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if (size < payload_size + 12) {
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error_report("milkymist_minimac: received too big ethernet frame");
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error_report("milkymist_minimac2: received too big ethernet frame");
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return 0;
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}
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@ -231,115 +228,102 @@ static size_t assemble_frame(uint8_t *buf, size_t size,
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return payload_size + 12;
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}
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static void minimac_tx(MilkymistMinimacState *s)
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static void minimac2_tx(MilkymistMinimac2State *s)
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{
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uint8_t buf[MINIMAC_MTU];
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uint32_t txcount = s->regs[R_TXCOUNT];
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/* do nothing if transmission logic is in reset */
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if (s->regs[R_SETUP] & SETUP_TX_RST) {
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return;
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}
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uint8_t *buf = s->tx_buf;
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if (txcount < 64) {
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error_report("milkymist_minimac: ethernet frame too small (%u < %u)\n",
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error_report("milkymist_minimac2: ethernet frame too small (%u < %u)\n",
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txcount, 64);
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return;
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goto err;
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}
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if (txcount > MINIMAC_MTU) {
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error_report("milkymist_minimac: MTU exceeded (%u > %u)\n",
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txcount, MINIMAC_MTU);
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return;
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if (txcount > MINIMAC2_MTU) {
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error_report("milkymist_minimac2: MTU exceeded (%u > %u)\n",
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txcount, MINIMAC2_MTU);
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goto err;
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}
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/* dma */
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cpu_physical_memory_read(s->regs[R_TXADDR], buf, txcount);
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if (memcmp(buf, preamble_sfd, 8) != 0) {
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error_report("milkymist_minimac: frame doesn't contain the preamble "
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error_report("milkymist_minimac2: frame doesn't contain the preamble "
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"and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)\n",
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buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
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return;
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goto err;
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}
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trace_milkymist_minimac_tx_frame(txcount - 12);
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trace_milkymist_minimac2_tx_frame(txcount - 12);
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/* send packet, skipping preamble and sfd */
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qemu_send_packet_raw(&s->nic->nc, buf + 8, txcount - 12);
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s->regs[R_TXCOUNT] = 0;
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trace_milkymist_minimac_pulse_irq_tx();
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err:
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trace_milkymist_minimac2_pulse_irq_tx();
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qemu_irq_pulse(s->tx_irq);
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}
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static ssize_t minimac_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
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static void update_rx_interrupt(MilkymistMinimac2State *s)
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{
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MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
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if (s->regs[R_STATE0] == STATE_PENDING
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|| s->regs[R_STATE1] == STATE_PENDING) {
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trace_milkymist_minimac2_raise_irq_rx();
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qemu_irq_raise(s->rx_irq);
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} else {
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trace_milkymist_minimac2_lower_irq_rx();
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qemu_irq_lower(s->rx_irq);
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}
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}
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static ssize_t minimac2_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
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{
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MilkymistMinimac2State *s = DO_UPCAST(NICState, nc, nc)->opaque;
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uint32_t r_addr;
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uint32_t r_count;
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uint32_t r_state;
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uint8_t *rx_buf;
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uint8_t frame_buf[MINIMAC_MTU];
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size_t frame_size;
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trace_milkymist_minimac_rx_frame(buf, size);
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/* discard frames if nic is in reset */
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if (s->regs[R_SETUP] & SETUP_RX_RST) {
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return size;
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}
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trace_milkymist_minimac2_rx_frame(buf, size);
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/* choose appropriate slot */
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if (s->regs[R_STATE0] == STATE_LOADED) {
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r_addr = R_ADDR0;
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r_count = R_COUNT0;
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r_state = R_STATE0;
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rx_buf = s->rx0_buf;
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} else if (s->regs[R_STATE1] == STATE_LOADED) {
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r_addr = R_ADDR1;
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r_count = R_COUNT1;
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r_state = R_STATE1;
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} else if (s->regs[R_STATE2] == STATE_LOADED) {
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r_addr = R_ADDR2;
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r_count = R_COUNT2;
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r_state = R_STATE2;
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} else if (s->regs[R_STATE3] == STATE_LOADED) {
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r_addr = R_ADDR3;
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r_count = R_COUNT3;
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r_state = R_STATE3;
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rx_buf = s->rx1_buf;
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} else {
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trace_milkymist_minimac_drop_rx_frame(buf);
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trace_milkymist_minimac2_drop_rx_frame(buf);
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return size;
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}
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/* assemble frame */
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frame_size = assemble_frame(frame_buf, sizeof(frame_buf), buf, size);
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frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
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if (frame_size == 0) {
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return size;
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}
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trace_milkymist_minimac_rx_transfer(buf, frame_size);
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/* do dma */
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cpu_physical_memory_write(s->regs[r_addr], frame_buf, frame_size);
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trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
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/* update slot */
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s->regs[r_count] = frame_size;
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s->regs[r_state] = STATE_PENDING;
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trace_milkymist_minimac_pulse_irq_rx();
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qemu_irq_pulse(s->rx_irq);
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update_rx_interrupt(s);
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return size;
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}
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static uint32_t
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minimac_read(void *opaque, target_phys_addr_t addr)
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minimac2_read(void *opaque, target_phys_addr_t addr)
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{
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MilkymistMinimacState *s = opaque;
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MilkymistMinimac2State *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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@ -347,39 +331,30 @@ minimac_read(void *opaque, target_phys_addr_t addr)
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case R_SETUP:
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case R_MDIO:
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case R_STATE0:
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case R_ADDR0:
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case R_COUNT0:
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case R_STATE1:
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case R_ADDR1:
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case R_COUNT1:
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case R_STATE2:
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case R_ADDR2:
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case R_COUNT2:
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case R_STATE3:
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case R_ADDR3:
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case R_COUNT3:
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case R_TXADDR:
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case R_TXCOUNT:
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r = s->regs[addr];
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break;
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default:
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error_report("milkymist_minimac: read access to unknown register 0x"
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error_report("milkymist_minimac2: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_milkymist_minimac_memory_read(addr << 2, r);
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trace_milkymist_minimac2_memory_read(addr << 2, r);
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return r;
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}
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static void
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minimac_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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MilkymistMinimacState *s = opaque;
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MilkymistMinimac2State *s = opaque;
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trace_milkymist_minimac_memory_read(addr, value);
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trace_milkymist_minimac2_memory_read(addr, value);
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addr >>= 2;
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switch (addr) {
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@ -394,58 +369,47 @@ minimac_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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s->regs[R_MDIO] &= ~mdio_di;
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}
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minimac_update_mdio(s);
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minimac2_update_mdio(s);
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} break;
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case R_TXCOUNT:
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s->regs[addr] = value;
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if (value > 0) {
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minimac_tx(s);
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minimac2_tx(s);
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}
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break;
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case R_SETUP:
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case R_STATE0:
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case R_ADDR0:
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case R_COUNT0:
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case R_STATE1:
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case R_ADDR1:
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s->regs[addr] = value;
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update_rx_interrupt(s);
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break;
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case R_SETUP:
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case R_COUNT0:
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case R_COUNT1:
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case R_STATE2:
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||||
case R_ADDR2:
|
||||
case R_COUNT2:
|
||||
case R_STATE3:
|
||||
case R_ADDR3:
|
||||
case R_COUNT3:
|
||||
case R_TXADDR:
|
||||
s->regs[addr] = value;
|
||||
break;
|
||||
|
||||
default:
|
||||
error_report("milkymist_minimac: write access to unknown register 0x"
|
||||
error_report("milkymist_minimac2: write access to unknown register 0x"
|
||||
TARGET_FMT_plx, addr << 2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc * const minimac_read_fn[] = {
|
||||
static CPUReadMemoryFunc * const minimac2_read_fn[] = {
|
||||
NULL,
|
||||
NULL,
|
||||
&minimac_read,
|
||||
&minimac2_read,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc * const minimac_write_fn[] = {
|
||||
static CPUWriteMemoryFunc * const minimac2_write_fn[] = {
|
||||
NULL,
|
||||
NULL,
|
||||
&minimac_write,
|
||||
&minimac2_write,
|
||||
};
|
||||
|
||||
static int minimac_can_rx(VLANClientState *nc)
|
||||
static int minimac2_can_rx(VLANClientState *nc)
|
||||
{
|
||||
MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
||||
|
||||
/* discard frames if nic is in reset */
|
||||
if (s->regs[R_SETUP] & SETUP_RX_RST) {
|
||||
return 1;
|
||||
}
|
||||
MilkymistMinimac2State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
||||
|
||||
if (s->regs[R_STATE0] == STATE_LOADED) {
|
||||
return 1;
|
||||
|
|
@ -453,27 +417,21 @@ static int minimac_can_rx(VLANClientState *nc)
|
|||
if (s->regs[R_STATE1] == STATE_LOADED) {
|
||||
return 1;
|
||||
}
|
||||
if (s->regs[R_STATE2] == STATE_LOADED) {
|
||||
return 1;
|
||||
}
|
||||
if (s->regs[R_STATE3] == STATE_LOADED) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void minimac_cleanup(VLANClientState *nc)
|
||||
static void minimac2_cleanup(VLANClientState *nc)
|
||||
{
|
||||
MilkymistMinimacState *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
||||
MilkymistMinimac2State *s = DO_UPCAST(NICState, nc, nc)->opaque;
|
||||
|
||||
s->nic = NULL;
|
||||
}
|
||||
|
||||
static void milkymist_minimac_reset(DeviceState *d)
|
||||
static void milkymist_minimac2_reset(DeviceState *d)
|
||||
{
|
||||
MilkymistMinimacState *s =
|
||||
container_of(d, MilkymistMinimacState, busdev.qdev);
|
||||
MilkymistMinimac2State *s =
|
||||
container_of(d, MilkymistMinimac2State, busdev.qdev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < R_MAX; i++) {
|
||||
|
|
@ -488,81 +446,94 @@ static void milkymist_minimac_reset(DeviceState *d)
|
|||
s->phy_regs[R_PHY_ID2] = 0x161a;
|
||||
}
|
||||
|
||||
static NetClientInfo net_milkymist_minimac_info = {
|
||||
static NetClientInfo net_milkymist_minimac2_info = {
|
||||
.type = NET_CLIENT_TYPE_NIC,
|
||||
.size = sizeof(NICState),
|
||||
.can_receive = minimac_can_rx,
|
||||
.receive = minimac_rx,
|
||||
.cleanup = minimac_cleanup,
|
||||
.can_receive = minimac2_can_rx,
|
||||
.receive = minimac2_rx,
|
||||
.cleanup = minimac2_cleanup,
|
||||
};
|
||||
|
||||
static int milkymist_minimac_init(SysBusDevice *dev)
|
||||
static int milkymist_minimac2_init(SysBusDevice *dev)
|
||||
{
|
||||
MilkymistMinimacState *s = FROM_SYSBUS(typeof(*s), dev);
|
||||
MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev);
|
||||
int regs;
|
||||
ram_addr_t buffers;
|
||||
size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
|
||||
|
||||
sysbus_init_irq(dev, &s->rx_irq);
|
||||
sysbus_init_irq(dev, &s->tx_irq);
|
||||
|
||||
regs = cpu_register_io_memory(minimac_read_fn, minimac_write_fn, s,
|
||||
regs = cpu_register_io_memory(minimac2_read_fn, minimac2_write_fn, s,
|
||||
DEVICE_NATIVE_ENDIAN);
|
||||
sysbus_init_mmio(dev, R_MAX * 4, regs);
|
||||
|
||||
/* register buffers memory */
|
||||
buffers = qemu_ram_alloc(NULL, "milkymist_minimac2.buffers", buffers_size);
|
||||
s->rx0_buf = qemu_get_ram_ptr(buffers);
|
||||
s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
|
||||
s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
|
||||
|
||||
cpu_register_physical_memory(s->buffers_base, buffers_size,
|
||||
buffers | IO_MEM_RAM);
|
||||
|
||||
qemu_macaddr_default_if_unset(&s->conf.macaddr);
|
||||
s->nic = qemu_new_nic(&net_milkymist_minimac_info, &s->conf,
|
||||
s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
|
||||
dev->qdev.info->name, dev->qdev.id, s);
|
||||
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_milkymist_minimac_mdio = {
|
||||
.name = "milkymist_minimac_mdio",
|
||||
static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
|
||||
.name = "milkymist-minimac2-mdio",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_INT32(last_clk, MilkymistMinimacMdioState),
|
||||
VMSTATE_INT32(count, MilkymistMinimacMdioState),
|
||||
VMSTATE_UINT32(data, MilkymistMinimacMdioState),
|
||||
VMSTATE_UINT16(data_out, MilkymistMinimacMdioState),
|
||||
VMSTATE_INT32(state, MilkymistMinimacMdioState),
|
||||
VMSTATE_UINT8(phy_addr, MilkymistMinimacMdioState),
|
||||
VMSTATE_UINT8(reg_addr, MilkymistMinimacMdioState),
|
||||
VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
|
||||
VMSTATE_INT32(count, MilkymistMinimac2MdioState),
|
||||
VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
|
||||
VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
|
||||
VMSTATE_INT32(state, MilkymistMinimac2MdioState),
|
||||
VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
|
||||
VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_milkymist_minimac = {
|
||||
.name = "milkymist-minimac",
|
||||
static const VMStateDescription vmstate_milkymist_minimac2 = {
|
||||
.name = "milkymist-minimac2",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(regs, MilkymistMinimacState, R_MAX),
|
||||
VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimacState, R_PHY_MAX),
|
||||
VMSTATE_STRUCT(mdio, MilkymistMinimacState, 0,
|
||||
vmstate_milkymist_minimac_mdio, MilkymistMinimacMdioState),
|
||||
VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
|
||||
VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
|
||||
VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
|
||||
vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static SysBusDeviceInfo milkymist_minimac_info = {
|
||||
.init = milkymist_minimac_init,
|
||||
.qdev.name = "milkymist-minimac",
|
||||
.qdev.size = sizeof(MilkymistMinimacState),
|
||||
.qdev.vmsd = &vmstate_milkymist_minimac,
|
||||
.qdev.reset = milkymist_minimac_reset,
|
||||
static SysBusDeviceInfo milkymist_minimac2_info = {
|
||||
.init = milkymist_minimac2_init,
|
||||
.qdev.name = "milkymist-minimac2",
|
||||
.qdev.size = sizeof(MilkymistMinimac2State),
|
||||
.qdev.vmsd = &vmstate_milkymist_minimac2,
|
||||
.qdev.reset = milkymist_minimac2_reset,
|
||||
.qdev.props = (Property[]) {
|
||||
DEFINE_NIC_PROPERTIES(MilkymistMinimacState, conf),
|
||||
DEFINE_PROP_STRING("phy_model", MilkymistMinimacState, phy_model),
|
||||
DEFINE_PROP_TADDR("buffers_base", MilkymistMinimac2State,
|
||||
buffers_base, 0),
|
||||
DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
|
||||
DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
}
|
||||
};
|
||||
|
||||
static void milkymist_minimac_register(void)
|
||||
static void milkymist_minimac2_register(void)
|
||||
{
|
||||
sysbus_register_withprop(&milkymist_minimac_info);
|
||||
sysbus_register_withprop(&milkymist_minimac2_info);
|
||||
}
|
||||
|
||||
device_init(milkymist_minimac_register)
|
||||
device_init(milkymist_minimac2_register)
|
||||
|
|
@ -156,7 +156,7 @@ milkymist_init(ram_addr_t ram_size_not_used,
|
|||
milkymist_ac97_create(0x60005000, irq[5], irq[6], irq[7], irq[8]);
|
||||
milkymist_pfpu_create(0x60006000, irq[9]);
|
||||
milkymist_tmu2_create(0x60007000, irq[10]);
|
||||
milkymist_minimac_create(0x60008000, irq[11], irq[12]);
|
||||
milkymist_minimac2_create(0x60008000, 0x30000000, irq[11], irq[12]);
|
||||
milkymist_softusb_create(0x6000f000, irq[17],
|
||||
0x20000000, 0x1000, 0x20020000, 0x2000);
|
||||
|
||||
|
|
|
|||
23
trace-events
23
trace-events
|
|
@ -308,17 +308,18 @@ disable milkymist_hpdmc_memory_write(uint32_t addr, uint32_t value) "addr=%08x v
|
|||
disable milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
|
||||
disable milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
|
||||
|
||||
# hw/milkymist-minimac.c
|
||||
disable milkymist_minimac_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
|
||||
disable milkymist_minimac_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
|
||||
disable milkymist_minimac_mdio_write(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
|
||||
disable milkymist_minimac_mdio_read(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
|
||||
disable milkymist_minimac_tx_frame(uint32_t length) "length %u"
|
||||
disable milkymist_minimac_rx_frame(const void *buf, uint32_t length) "buf %p length %u"
|
||||
disable milkymist_minimac_drop_rx_frame(const void *buf) "buf %p"
|
||||
disable milkymist_minimac_rx_transfer(const void *buf, uint32_t length) "buf %p length %d"
|
||||
disable milkymist_minimac_pulse_irq_rx(void) "Pulse IRQ RX"
|
||||
disable milkymist_minimac_pulse_irq_tx(void) "Pulse IRQ TX"
|
||||
# hw/milkymist-minimac2.c
|
||||
disable milkymist_minimac2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
|
||||
disable milkymist_minimac2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
|
||||
disable milkymist_minimac2_mdio_write(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
|
||||
disable milkymist_minimac2_mdio_read(uint8_t phy_addr, uint8_t addr, uint16_t value) "phy_addr %02x addr %02x value %04x"
|
||||
disable milkymist_minimac2_tx_frame(uint32_t length) "length %u"
|
||||
disable milkymist_minimac2_rx_frame(const void *buf, uint32_t length) "buf %p length %u"
|
||||
disable milkymist_minimac2_drop_rx_frame(const void *buf) "buf %p"
|
||||
disable milkymist_minimac2_rx_transfer(const void *buf, uint32_t length) "buf %p length %d"
|
||||
disable milkymist_minimac2_raise_irq_rx(void) "Raise IRQ RX"
|
||||
disable milkymist_minimac2_lower_irq_rx(void) "Lower IRQ RX"
|
||||
disable milkymist_minimac2_pulse_irq_tx(void) "Pulse IRQ TX"
|
||||
|
||||
# hw/milkymist-pfpu.c
|
||||
disable milkymist_pfpu_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
|
||||
|
|
|
|||
Loading…
Reference in New Issue