mirror of https://github.com/xemu-project/xemu.git
tests/tcg: enable arm softmmu tests
To make it easier to test 32 bit Arm softmmu issues implement a basic boot.S so we can build the multiarch tests. Currently CHECK_UNALIGNED is disabled as I haven't got the right magic set for it to work. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231120150833.2552739-12-alex.bennee@linaro.org>
This commit is contained in:
Alex Bennée
parent
e8368b1c95
commit
56611e17d2
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@ -8,20 +8,64 @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm/system
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# Set search path for all sources
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# Set search path for all sources
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VPATH += $(ARM_SRC)
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VPATH += $(ARM_SRC)
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ARM_TESTS=test-armv6m-undef
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TESTS += $(ARM_TESTS)
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LDFLAGS+=-nostdlib -N -static
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%: %.S %.ld
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$(CC) $(CFLAGS) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) -T $(ARM_SRC)/$@.ld
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# Specific Test Rules
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# Specific Test Rules
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test-armv6m-undef: EXTRA_CFLAGS+=-mcpu=cortex-m0 -mfloat-abi=soft -Wl,--build-id=none -x assembler-with-cpp
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test-armv6m-undef: test-armv6m-undef.S
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$(CC) -mcpu=cortex-m0 -mfloat-abi=soft \
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-Wl,--build-id=none -x assembler-with-cpp \
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$< -o $@ -nostdlib -N -static \
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-T $(ARM_SRC)/$@.ld
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run-test-armv6m-undef: QEMU_OPTS+=-semihosting -M microbit -kernel
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run-test-armv6m-undef: QEMU_OPTS+=-semihosting -M microbit -kernel
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# We don't currently support the multiarch system tests
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ARM_TESTS+=test-armv6m-undef
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undefine MULTIARCH_TESTS
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# These objects provide the basic boot code and helper functions for all tests
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CRT_OBJS=boot.o
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ARM_TEST_SRCS=$(wildcard $(ARM_SRC)/*.c)
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ARM_TESTS+=$(patsubst $(ARM_SRC)/%.c, %, $(ARM_TEST_SRCS))
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CRT_PATH=$(ARM_SRC)
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LINK_SCRIPT=$(ARM_SRC)/kernel.ld
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LDFLAGS=-Wl,-T$(LINK_SCRIPT)
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CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC)
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LDFLAGS+=-static -nostdlib -N $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
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# building head blobs
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.PRECIOUS: $(CRT_OBJS)
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%.o: $(ARM_SRC)/%.S
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$(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@
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# Build and link the tests
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%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
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$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
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memory: CFLAGS+=-DCHECK_UNALIGNED=0
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# Running
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QEMU_BASE_MACHINE=-M virt -cpu max -display none
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QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel
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# Simple Record/Replay Test
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.PHONY: memory-record
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run-memory-record: memory-record memory
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$(call run-test, $<, \
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$(QEMU) -monitor none -display none \
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-chardev file$(COMMA)path=$<.out$(COMMA)id=output \
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-icount shift=5$(COMMA)rr=record$(COMMA)rrfile=record.bin \
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$(QEMU_OPTS) memory)
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.PHONY: memory-replay
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run-memory-replay: memory-replay run-memory-record
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$(call run-test, $<, \
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$(QEMU) -monitor none -display none \
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-chardev file$(COMMA)path=$<.out$(COMMA)id=output \
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-icount shift=5$(COMMA)rr=replay$(COMMA)rrfile=record.bin \
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$(QEMU_OPTS) memory)
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EXTRA_RUNS+=run-memory-replay
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TESTS += $(ARM_TESTS) $(MULTIARCH_TESTS)
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EXTRA_RUNS+=$(MULTIARCH_RUNS)
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@ -0,0 +1,319 @@
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/*
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* Minimal ArmV7 system boot code.
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*
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* Using semihosting for serial output and exit functions.
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*/
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/*
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* Semihosting interface on ARM AArch32
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* R0 - semihosting call number
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* R1 - semihosting parameter
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*/
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#define semihosting_call svc 0x123456
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#define SYS_WRITEC 0x03 /* character to debug channel */
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#define SYS_WRITE0 0x04 /* string to debug channel */
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#define SYS_EXIT 0x18
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#define ADP_Stopped_ApplicationExit 0x20026
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#define ADP_Stopped_InternalError 0x20024
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/*
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* Helper macro for annotating functions with elf type and size.
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*/
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.macro endf name
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.global \name
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.type \name, %function
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.size \name, . - \name
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.endm
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.section .interrupt_vector, "ax"
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.align 5
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vector_table:
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b reset /* reset vector */
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b undef_instr /* undefined instruction vector */
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b software_intr /* software interrupt vector */
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b prefetch_abort /* prefetch abort vector */
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b data_abort /* data abort vector */
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nop /* reserved */
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b IRQ_handler /* IRQ vector */
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b FIQ_handler /* FIQ vector */
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endf vector_table
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.text
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__start:
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ldr r0, =vector_table
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mcr p15, 0, r0, c12, c0, 0 /* Set up VBAR */
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ldr sp, =stack_end /* Set up the stack */
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bl mmu_setup /* Set up the MMU */
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bl main /* Jump to main */
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endf __start
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_exit:
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cmp r0, #0
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ite EQ // if-then-else. "EQ" is for if equal, else otherwise
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ldreq r1, =ADP_Stopped_ApplicationExit // if r0 == 0
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ldrne r1, =ADP_Stopped_InternalError // else
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mov r0, #SYS_EXIT
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semihosting_call
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endf _exit
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/*
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* Helper Functions
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*/
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mmu_setup:
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/*
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* The MMU setup for this is very simple using two stage one
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* translations. The first 1Mb section points to the text
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* section and the second points to the data and rss.
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* Currently the fattest test only needs ~50k for that so we
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* have plenty of space.
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*
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* The short descriptor Section format is as follows:
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*
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* PA[31:20] - Section Base Address
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* NS[19] - Non-secure bit
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* 0[18] - Section (1 for Super Section)
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* nG[17] - Not global bit
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* S[16] - Shareable
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* TEX[14:12] - Memory Region Attributes
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* AP[15, 11:10] - Access Permission Bits
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* IMPDEF[9]
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* Domain[8:5]
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* XN[4] - Execute never bit
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* C[3] - Memory Region Attributes
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* B[2] - Memory Region Attributes
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* 1[1]
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* PXN[0] - Privileged Execute Never
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*
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* r0 - point at the table
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* r1 - address
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* r2 - entry
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* r3 - common section bits
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* r4 - scratch
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*/
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/*
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* Memory Region Bits
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*
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* TEX[14:12] = 000
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* C[3] = 1
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* B[2] = 1
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*
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* Outer and Inner WB, no write allocate
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*/
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mov r3, #0
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ldr r4, =(3 << 2)
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orr r3, r4, r4
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/* Section bit */
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orr r3, r3, #2
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/* Page table setup (identity mapping). */
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ldr r0, =ttb
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/* First block: .text/RO/execute enabled */
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ldr r1, =.text
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ldr r2, =0xFFF00000 /* 1MB block alignment */
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and r2, r1, r2
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orr r2, r2, r3 /* common bits */
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orr r2, r2, #(1 << 15) /* AP[2] = 1 */
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orr r2, r2, #(1 << 10) /* AP[0] = 1 => RO @ PL1 */
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lsr r4, r2, #(20 - 2)
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str r2, [r0, r4, lsl #0] /* write entry */
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/* Second block: .data/RW/no execute */
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ldr r1, =.data
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ldr r2, =0xFFF00000 /* 1MB block alignment */
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and r2, r1, r2
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orr r2, r2, r3 /* common bits */
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orr r2, r2, #(1 << 10) /* AP[0] = 1 => RW @ PL1 */
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orr r2, r2, #(1 << 4) /* XN[4] => no execute */
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lsr r4, r2, #(20 - 2)
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str r2, [r0, r4, lsl #0] /* write entry */
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/*
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* DACR - Domain Control
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*
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* Enable client mode for domain 0 (we don't use any others)
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*/
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ldr r0, =0x1
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mcr p15, 0, r0, c3, c0, 0
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/*
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* TTCBR - Translation Table Base Control Register
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*
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* EAE[31] = 0, 32-bit translation, short descriptor format
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* N[2:0] = 5 ( TTBRO uses 31:14-5 => 9 bit lookup stage )
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*/
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ldr r0, =0x5
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mcr p15, 0, r0, c1, c0, 2
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/*
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* TTBR0 -Translation Table Base Register 0
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*
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* [31:9] = Base address of table
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*
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* QEMU doesn't really care about the cache sharing
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* attributes so we don't need to either.
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*/
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ldr r0, =ttb
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mcr p15, 0, r0, c2, c0, 0
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/*
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* SCTLR- System Control Register
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*
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* TE[30] = 0, exceptions to A32 state
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* AFE[29] = 0, AP[0] is the access permissions bit
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* EE[25] = 0, Little-endian
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* WXN[19] = 0 = no effect, Write does not imply XN (execute never)
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* I[12] = Instruction cachability control
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* C[2] = Data cachability control
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* M[0] = 1, enable stage 1 address translation for EL0/1
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*
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* At this point virtual memory is enabled.
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*/
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ldr r0, =0x1005
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mcr p15, 0, r0, c1, c0, 0
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isb
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mov pc, lr /* done, return to caller */
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endf mmu_setup
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/* Output a single character to serial port */
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__sys_outc:
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STMFD sp!, {r0-r1} // push r0, r1 onto stack
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mov r1, sp
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mov r0, #SYS_WRITEC
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semihosting_call
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LDMFD sp!, {r0-r1} // pop r0, r1 from stack
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bx lr
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endf __sys_outc
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reset:
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ldr r1, =reset_error
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b exception_handler
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endf reset
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undef_instr:
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ldr r1, =undef_intr_error
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b exception_handler
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endf undef_instr
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software_intr:
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ldr r1, =software_intr_error
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b exception_handler
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endf software_intr
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prefetch_abort:
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ldr r1, =prefetch_abort_error
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b exception_handler
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endf prefetch_abort
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data_abort:
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ldr r1, =data_abort_error
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b exception_handler
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endf data_abort
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IRQ_handler:
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ldr r1, =irq_error
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b exception_handler
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endf IRQ_handler
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FIQ_handler:
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ldr r1, =fiq_error
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b exception_handler
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endf FIQ_handler
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/*
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* Initiate a exit semihosting call whenever there is any exception
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* r1 already holds the string.
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*/
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exception_handler:
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mov r0, #SYS_WRITE0
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semihosting_call
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mov r0, #SYS_EXIT
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mov r1, #1
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semihosting_call
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endf exception_handler
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/*
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* We implement a stub raise() function which errors out as tests
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* shouldn't trigger maths errors.
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*/
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.global raise
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raise:
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mov r0, #SYS_WRITE0
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ldr r1, =maths_error
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semihosting_call
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mov r0, #SYS_EXIT
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ldr r1, =ADP_Stopped_InternalError
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semihosting_call
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endf raise
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.data
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.data
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reset_error:
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.ascii "Reset exception occurred.\n\0"
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undef_intr_error:
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.ascii "Undefined Instruction Exception Occurred.\n\0"
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software_intr_error:
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.ascii "Software Interrupt Occurred.\n\0"
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prefetch_abort_error:
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.ascii "Prefetch Abort Occurred.\n\0"
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data_abort_error:
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.ascii "Data Abort Occurred.\n\0"
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irq_error:
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.ascii "IRQ exception occurred.\n\0"
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fiq_error:
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.ascii "FIQ exception occurred.\n\0"
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maths_error:
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.ascii "Software maths exception.\n\0"
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/*
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* 1st Stage Translation table
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||||||
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* 4096 entries, indexed by [31:20]
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* each entry covers 1Mb of address space
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* aligned on 16kb
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*/
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.align 15
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ttb:
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.space (4096 * 4), 0
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.align 12
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/* Space for stack */
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||||||
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.align 5
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||||||
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.section .bss
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stack:
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||||||
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.space 65536, 0
|
||||||
|
stack_end:
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
ENTRY(__start)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* virt machine, RAM starts at 1gb */
|
||||||
|
. = (1 << 30);
|
||||||
|
.text : {
|
||||||
|
*(.text)
|
||||||
|
}
|
||||||
|
.rodata : {
|
||||||
|
*(.rodata)
|
||||||
|
}
|
||||||
|
/* align r/w section to next 2mb */
|
||||||
|
. = ALIGN(1 << 21);
|
||||||
|
.data : {
|
||||||
|
*(.data)
|
||||||
|
}
|
||||||
|
.bss : {
|
||||||
|
*(.bss)
|
||||||
|
}
|
||||||
|
/DISCARD/ : {
|
||||||
|
*(.ARM.attributes)
|
||||||
|
}
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue