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target/arm: handle A-profile semihosting at translate time 

As for the other semihosting calls we can resolve this at translate
time.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190913151845.12582-4-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2019-09-19 14:18:40 +01:00 committed by Peter Maydell
parent 376214e4f4
commit 5651697f1f
1 changed files with 15 additions and 4 deletions
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19
target/arm/translate.c
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@ -10222,14 +10222,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
} }
/* /*
* Supervisor call * Supervisor call - both T32 & A32 come here so we need to check
* which mode we are in when checking for semihosting.
*/ */
static bool trans_SVC(DisasContext *s, arg_SVC *a) static bool trans_SVC(DisasContext *s, arg_SVC *a)
{ {
gen_set_pc_im(s, s->base.pc_next); const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456;
s->svc_imm = a->imm;
s->base.is_jmp = DISAS_SWI; if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() &&
#ifndef CONFIG_USER_ONLY
!IS_USER(s) &&
#endif
(a->imm == semihost_imm)) {
gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
} else {
gen_set_pc_im(s, s->base.pc_next);
s->svc_imm = a->imm;
s->base.is_jmp = DISAS_SWI;
}
return true; return true;
} }