mirror of https://github.com/xemu-project/xemu.git
target/arm: Update CNTVCT_EL0 for VHE
The virtual offset may be 0 depending on EL, E2H and TGE. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2515,9 +2515,31 @@ static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
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return gt_get_countervalue(env);
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}
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static uint64_t gt_virt_cnt_offset(CPUARMState *env)
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{
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uint64_t hcr;
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switch (arm_current_el(env)) {
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case 2:
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hcr = arm_hcr_el2_eff(env);
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if (hcr & HCR_E2H) {
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return 0;
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}
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break;
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case 0:
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hcr = arm_hcr_el2_eff(env);
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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return 0;
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}
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break;
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}
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return env->cp15.cntvoff_el2;
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}
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static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
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return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
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}
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static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -2532,7 +2554,13 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
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int timeridx)
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{
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uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
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uint64_t offset = 0;
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switch (timeridx) {
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case GTIMER_VIRT:
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offset = gt_virt_cnt_offset(env);
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break;
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}
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return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
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(gt_get_countervalue(env) - offset));
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@ -2542,7 +2570,13 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
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int timeridx,
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uint64_t value)
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{
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uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
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uint64_t offset = 0;
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switch (timeridx) {
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case GTIMER_VIRT:
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offset = gt_virt_cnt_offset(env);
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break;
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}
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trace_arm_gt_tval_write(timeridx, value);
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env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
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