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target/sparc: Implement FMAF, IMA, VIS3 and VIS4 extensions 

linux-user: Add ioctl for BLKBSZSET
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Merge tag 'pull-sp-20240605' of https://gitlab.com/rth7680/qemu into staging

target/sparc: Implement FMAF, IMA, VIS3 and VIS4 extensions
linux-user: Add ioctl for BLKBSZSET

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# gpg: Signature made Wed 05 Jun 2024 09:13:12 AM PDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-sp-20240605' of https://gitlab.com/rth7680/qemu: (38 commits)
  target/sparc: Enable VIS4 feature bit
  target/sparc: Implement monitor ASIs
  target/sparc: Implement MWAIT
  target/sparc: Implement SUBXC, SUBXCcc
  target/sparc: Implement FPMIN, FPMAX
  target/sparc: Implement VIS4 comparisons
  target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS
  target/sparc: Implement FALIGNDATAi
  target/sparc: Add feature bit for VIS4
  target/sparc: Implement IMA extension
  target/sparc: Enable VIS3 feature bit
  target/sparc: Implement XMULX
  target/sparc: Implement UMULXHI
  target/sparc: Implement PDISTN
  target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd
  target/sparc: Implement LZCNT
  target/sparc: Implement LDXEFSR
  target/sparc: Implement FSLL, FSRL, FSRA, FSLAS
  target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8
  target/sparc: Implement FPADDS, FPSUBS
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-06-05 10:24:03 -07:00
parent f1572ab947 b12b722743
commit 535ad16c5d
12 changed files with 1563 additions and 331 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
fpu/softfloat-specialize.c.inc
View File

@ -447,6 +447,17 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
} else {
return 1;
}
#elif defined(TARGET_SPARC)
/* Prefer SNaN over QNaN, order B then A. */
if (is_snan(b_cls)) {
return 1;
} else if (is_snan(a_cls)) {
return 0;
} else if (is_qnan(b_cls)) {
return 1;
} else {
return 0;
}
#elif defined(TARGET_XTENSA)
/*
* Xtensa has two NaN propagation modes.
@ -624,6 +635,26 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
}
return 3; /* default NaN */
#elif defined(TARGET_SPARC)
/* For (inf,0,nan) return c. */
if (infzero) {
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
return 2;
}
/* Prefer SNaN over QNaN, order C, B, A. */
if (is_snan(c_cls)) {
return 2;
} else if (is_snan(b_cls)) {
return 1;
} else if (is_snan(a_cls)) {
return 0;
} else if (is_qnan(c_cls)) {
return 2;
} else if (is_qnan(b_cls)) {
return 1;
} else {
return 0;
}
#elif defined(TARGET_XTENSA)
/*
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns

3
linux-user/elfload.c
View File

@ -1003,6 +1003,9 @@ static uint32_t get_elf_hwcap(void)
r |= features & CPU_FEATURE_FSMULD ? HWCAP_SPARC_FSMULD : 0;
r |= features & CPU_FEATURE_VIS1 ? HWCAP_SPARC_VIS : 0;
r |= features & CPU_FEATURE_VIS2 ? HWCAP_SPARC_VIS2 : 0;
r |= features & CPU_FEATURE_FMAF ? HWCAP_SPARC_FMAF : 0;
r |= features & CPU_FEATURE_VIS3 ? HWCAP_SPARC_VIS3 : 0;
r |= features & CPU_FEATURE_IMA ? HWCAP_SPARC_IMA : 0;
#endif
return r;

1
linux-user/ioctls.h
View File

@ -102,6 +102,7 @@
IOCTL(BLKRAGET, IOC_R, MK_PTR(TYPE_LONG))
IOCTL(BLKSSZGET, IOC_R, MK_PTR(TYPE_INT))
IOCTL(BLKBSZGET, IOC_R, MK_PTR(TYPE_INT))
IOCTL(BLKBSZSET, IOC_W, MK_PTR(TYPE_INT))
IOCTL_SPECIAL(BLKPG, IOC_W, do_ioctl_blkpg,
MK_PTR(MK_STRUCT(STRUCT_blkpg_ioctl_arg)))

4
target/sparc/asi.h
View File

@ -144,6 +144,8 @@
* ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4
* and later ASIs.
*/
#define ASI_MON_AIUP 0x12 /* (VIS4) Primary, user, monitor */
#define ASI_MON_AIUS 0x13 /* (VIS4) Secondary, user, monitor */
#define ASI_REAL 0x14 /* Real address, cacheable */
#define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */
#define ASI_REAL_IO 0x15 /* Real address, non-cacheable */
@ -257,6 +259,8 @@
#define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
#define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
#define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
#define ASI_MON_P 0x84 /* (VIS4) Primary, monitor */
#define ASI_MON_S 0x85 /* (VIS4) Secondary, monitor */
#define ASI_PIC 0xb0 /* (NG4) PIC registers */
#define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
#define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */

4
target/sparc/cpu-feature.h.inc
View File

@ -12,3 +12,7 @@ FEATURE(ASR17)
FEATURE(CACHE_CTRL)
FEATURE(POWERDOWN)
FEATURE(CASA)
FEATURE(FMAF)
FEATURE(VIS3)
FEATURE(IMA)
FEATURE(VIS4)

12
target/sparc/cpu.c
View File

@ -549,6 +549,10 @@ static const char * const feature_name[] = {
[CPU_FEATURE_BIT_HYPV] = "hypv",
[CPU_FEATURE_BIT_VIS1] = "vis1",
[CPU_FEATURE_BIT_VIS2] = "vis2",
[CPU_FEATURE_BIT_FMAF] = "fmaf",
[CPU_FEATURE_BIT_VIS3] = "vis3",
[CPU_FEATURE_BIT_IMA] = "ima",
[CPU_FEATURE_BIT_VIS4] = "vis4",
#else
[CPU_FEATURE_BIT_MUL] = "mul",
[CPU_FEATURE_BIT_DIV] = "div",
@ -877,6 +881,14 @@ static Property sparc_cpu_properties[] = {
CPU_FEATURE_BIT_VIS1, false),
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS2, false),
DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_FMAF, false),
DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS3, false),
DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_IMA, false),
DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_VIS4, false),
#else
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
CPU_FEATURE_BIT_MUL, false),

136
target/sparc/fop_helper.c
View File

@ -343,6 +343,90 @@ Int128 helper_fsqrtq(CPUSPARCState *env, Int128 src)
return f128_ret(ret);
}
float32 helper_fmadds(CPUSPARCState *env, float32 s1,
float32 s2, float32 s3, uint32_t op)
{
float32 ret = float32_muladd(s1, s2, s3, op, &env->fp_status);
check_ieee_exceptions(env, GETPC());
return ret;
}
float64 helper_fmaddd(CPUSPARCState *env, float64 s1,
float64 s2, float64 s3, uint32_t op)
{
float64 ret = float64_muladd(s1, s2, s3, op, &env->fp_status);
check_ieee_exceptions(env, GETPC());
return ret;
}
float32 helper_fnadds(CPUSPARCState *env, float32 src1, float32 src2)
{
float32 ret = float32_add(src1, src2, &env->fp_status);
/*
* NaN inputs or result do not get a sign change.
* Nor, apparently, does zero: on hardware, -(x + -x) yields +0.
*/
if (!float32_is_any_nan(ret) && !float32_is_zero(ret)) {
ret = float32_chs(ret);
}
check_ieee_exceptions(env, GETPC());
return ret;
}
float32 helper_fnmuls(CPUSPARCState *env, float32 src1, float32 src2)
{
float32 ret = float32_mul(src1, src2, &env->fp_status);
/* NaN inputs or result do not get a sign change. */
if (!float32_is_any_nan(ret)) {
ret = float32_chs(ret);
}
check_ieee_exceptions(env, GETPC());
return ret;
}
float64 helper_fnaddd(CPUSPARCState *env, float64 src1, float64 src2)
{
float64 ret = float64_add(src1, src2, &env->fp_status);
/*
* NaN inputs or result do not get a sign change.
* Nor, apparently, does zero: on hardware, -(x + -x) yields +0.
*/
if (!float64_is_any_nan(ret) && !float64_is_zero(ret)) {
ret = float64_chs(ret);
}
check_ieee_exceptions(env, GETPC());
return ret;
}
float64 helper_fnmuld(CPUSPARCState *env, float64 src1, float64 src2)
{
float64 ret = float64_mul(src1, src2, &env->fp_status);
/* NaN inputs or result do not get a sign change. */
if (!float64_is_any_nan(ret)) {
ret = float64_chs(ret);
}
check_ieee_exceptions(env, GETPC());
return ret;
}
float64 helper_fnsmuld(CPUSPARCState *env, float32 src1, float32 src2)
{
float64 ret = float64_mul(float32_to_float64(src1, &env->fp_status),
float32_to_float64(src2, &env->fp_status),
&env->fp_status);
/* NaN inputs or result do not get a sign change. */
if (!float64_is_any_nan(ret)) {
ret = float64_chs(ret);
}
check_ieee_exceptions(env, GETPC());
return ret;
}
static uint32_t finish_fcmp(CPUSPARCState *env, FloatRelation r, uintptr_t ra)
{
check_ieee_exceptions(env, ra);
@ -406,6 +490,52 @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
return finish_fcmp(env, r, GETPC());
}
uint32_t helper_flcmps(float32 src1, float32 src2)
{
/*
* FLCMP never raises an exception nor modifies any FSR fields.
* Perform the comparison with a dummy fp environment.
*/
float_status discard = { };
FloatRelation r = float32_compare_quiet(src1, src2, &discard);
switch (r) {
case float_relation_equal:
if (src2 == float32_zero && src1 != float32_zero) {
return 1; /* -0.0 < +0.0 */
}
return 0;
case float_relation_less:
return 1;
case float_relation_greater:
return 0;
case float_relation_unordered:
return float32_is_any_nan(src2) ? 3 : 2;
}
g_assert_not_reached();
}
uint32_t helper_flcmpd(float64 src1, float64 src2)
{
float_status discard = { };
FloatRelation r = float64_compare_quiet(src1, src2, &discard);
switch (r) {
case float_relation_equal:
if (src2 == float64_zero && src1 != float64_zero) {
return 1; /* -0.0 < +0.0 */
}
return 0;
case float_relation_less:
return 1;
case float_relation_greater:
return 0;
case float_relation_unordered:
return float64_is_any_nan(src2) ? 3 : 2;
}
g_assert_not_reached();
}
target_ulong cpu_get_fsr(CPUSPARCState *env)
{
target_ulong fsr = env->fsr | env->fsr_cexc_ftt;
@ -472,3 +602,9 @@ void helper_set_fsr_nofcc_noftt(CPUSPARCState *env, uint32_t fsr)
env->fsr_cexc_ftt |= fsr & FSR_CEXC_MASK;
set_fsr_nonsplit(env, fsr);
}
void helper_set_fsr_nofcc(CPUSPARCState *env, uint32_t fsr)
{
env->fsr_cexc_ftt = fsr & (FSR_CEXC_MASK | FSR_FTT_MASK);
set_fsr_nonsplit(env, fsr);
}

27
target/sparc/helper.h
View File

@ -40,6 +40,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif
DEF_HELPER_FLAGS_1(get_fsr, TCG_CALL_NO_WG_SE, tl, env)
DEF_HELPER_FLAGS_2(set_fsr_nofcc, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(set_fsr_nofcc_noftt, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_WG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_WG, f64, env, f64)
@ -50,12 +51,17 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
DEF_HELPER_2(raise_exception, noreturn, env, int)
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_5(fmaddd, TCG_CALL_NO_WG, f64, env, f64, f64, f64, i32)
DEF_HELPER_FLAGS_3(fnaddd, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fnmuld, TCG_CALL_NO_WG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(faddq, TCG_CALL_NO_WG, i128, env, i128, i128)
DEF_HELPER_FLAGS_3(fsubq, TCG_CALL_NO_WG, i128, env, i128, i128)
@ -66,8 +72,12 @@ DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_5(fmadds, TCG_CALL_NO_WG, f32, env, f32, f32, f32, i32)
DEF_HELPER_FLAGS_3(fnadds, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fnmuls, TCG_CALL_NO_WG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_WG, f64, env, f32, f32)
DEF_HELPER_FLAGS_3(fnsmuld, TCG_CALL_NO_WG, f64, env, f32, f32)
DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_WG, i128, env, f64, f64)
DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_WG, f64, env, s32)
@ -105,15 +115,28 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64)
DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(cmask8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmask16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(cmask32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmean16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fslas16, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fslas32, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#define VIS_CMPHELPER(name) \
DEF_HELPER_FLAGS_2(f##name##8, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \
i64, i64, i64) \
i64, i64, i64) \
DEF_HELPER_FLAGS_2(f##name##32, TCG_CALL_NO_RWG_SE, \
i64, i64, i64)
VIS_CMPHELPER(cmpgt)
VIS_CMPHELPER(cmpeq)
VIS_CMPHELPER(cmple)
VIS_CMPHELPER(cmpne)
VIS_CMPHELPER(cmpugt)
VIS_CMPHELPER(cmpule)
DEF_HELPER_FLAGS_2(xmulx, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(xmulxhi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#endif
#undef VIS_HELPER
#undef VIS_CMPHELPER

338
target/sparc/insns.decode
View File

@ -26,6 +26,15 @@ CALL 01 i:s30
## Major Opcode 10 -- integer, floating-point, vis, and system insns.
##
%dfp_rd 25:5 !function=extract_dfpreg
%dfp_rs1 14:5 !function=extract_dfpreg
%dfp_rs2 0:5 !function=extract_dfpreg
%dfp_rs3 9:5 !function=extract_dfpreg
%qfp_rd 25:5 !function=extract_qfpreg
%qfp_rs1 14:5 !function=extract_qfpreg
%qfp_rs2 0:5 !function=extract_qfpreg
&r_r_ri rd rs1 rs2_or_imm imm:bool
@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
@r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri
@ -37,11 +46,45 @@ CALL 01 i:s30
&r_r_r rd rs1 rs2
@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
@d_r_r .. ..... ...... rs1:5 . ........ rs2:5 \
&r_r_r rd=%dfp_rd
@r_d_d .. rd:5 ...... ..... . ........ ..... \
&r_r_r rs1=%dfp_rs1 rs2=%dfp_rs2
@d_r_d .. ..... ...... rs1:5 . ........ ..... \
&r_r_r rd=%dfp_rd rs2=%dfp_rs2
@d_d_d .. ..... ...... ..... . ........ ..... \
&r_r_r rd=%dfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2
@q_q_q .. ..... ...... ..... . ........ ..... \
&r_r_r rd=%qfp_rd rs1=%qfp_rs1 rs2=%qfp_rs2
@q_d_d .. ..... ...... ..... . ........ ..... \
&r_r_r rd=%qfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2
@r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r
@d_d_d_swap .. ..... ...... ..... . ........ ..... \
&r_r_r rd=%dfp_rd rs1=%dfp_rs2 rs2=%dfp_rs1
&r_r rd rs
@r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r
@r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r
@r_d2 .. rd:5 ...... ..... . ........ ..... &r_r rs=%dfp_rs2
@r_q2 .. rd:5 ...... ..... . ........ ..... &r_r rs=%qfp_rs2
@d_r2 .. ..... ...... ..... . ........ rs:5 &r_r rd=%dfp_rd
@q_r2 .. ..... ...... ..... . ........ rs:5 &r_r rd=%qfp_rd
@d_d1 .. ..... ...... ..... . ........ ..... \
&r_r rd=%dfp_rd rs=%dfp_rs1
@d_d2 .. ..... ...... ..... . ........ ..... \
&r_r rd=%dfp_rd rs=%dfp_rs2
@d_q2 .. ..... ...... ..... . ........ ..... \
&r_r rd=%dfp_rd rs=%qfp_rs2
@q_q2 .. ..... ...... ..... . ........ ..... \
&r_r rd=%qfp_rd rs=%qfp_rs2
@q_d2 .. ..... ...... ..... . ........ ..... \
&r_r rd=%qfp_rd rs=%dfp_rs2
&r_r_r_r rd rs1 rs2 rs3
@r_r_r_r .. rd:5 ...... rs1:5 rs3:5 .... rs2:5 &r_r_r_r
@d_d_d_d .. ..... ...... ..... ..... .... ..... \
&r_r_r_r rd=%dfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2 rs3=%dfp_rs3
{
[
@ -81,6 +124,7 @@ CALL 01 i:s30
WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri
WRSTICK 10 11000 110000 ..... . ............. @n_r_ri
WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri
WRMWAIT 10 11100 110000 ..... . ............. @n_r_ri
]
# Before v8, rs1==0 was WRY, and the rest executed as nop.
[
@ -241,68 +285,89 @@ DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000
FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2
FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2
FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @r_r2
FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @d_d2
FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @q_q2
FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2
FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2
FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @r_r2
FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @d_d2
FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @q_q2
FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
FABSq 10 ..... 110100 00000 0 0000 1011 ..... @r_r2
FABSd 10 ..... 110100 00000 0 0000 1010 ..... @d_d2
FABSq 10 ..... 110100 00000 0 0000 1011 ..... @q_q2
FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2
FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2
FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2
FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @d_d2
FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @q_q2
FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r
FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r
FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r
FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @d_d_d
FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @q_q_q
FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r
FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r
FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r
FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @d_d_d
FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @q_q_q
FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r
FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r
FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r
FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @d_d_d
FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @q_q_q
FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r
FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r
FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r
FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r
FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r
FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @d_d_d
FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @q_q_q
FNADDs 10 ..... 110100 ..... 0 0101 0001 ..... @r_r_r
FNADDd 10 ..... 110100 ..... 0 0101 0010 ..... @d_d_d
FNMULs 10 ..... 110100 ..... 0 0101 1001 ..... @r_r_r
FNMULd 10 ..... 110100 ..... 0 0101 1010 ..... @d_d_d
FHADDs 10 ..... 110100 ..... 0 0110 0001 ..... @r_r_r
FHADDd 10 ..... 110100 ..... 0 0110 0010 ..... @d_d_d
FHSUBs 10 ..... 110100 ..... 0 0110 0101 ..... @r_r_r
FHSUBd 10 ..... 110100 ..... 0 0110 0110 ..... @d_d_d
FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @d_r_r
FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @q_d_d
FNHADDs 10 ..... 110100 ..... 0 0111 0001 ..... @r_r_r
FNHADDd 10 ..... 110100 ..... 0 0111 0010 ..... @d_d_d
FNsMULd 10 ..... 110100 ..... 0 0111 1001 ..... @d_r_r
FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2
FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2
FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2
FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_d2
FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_q2
FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2
FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2
FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @r_r2
FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @d_r2
FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @q_r2
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2
FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2
FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2
FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2
FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2
FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2
FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2
FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @r_r2
FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_d2
FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_q2
FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @d_r2
FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @d_r2
FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @d_q2
FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @q_r2
FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @q_r2
FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @q_d2
FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2
FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2
FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2
FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_d2
FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_q2
FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5
FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5
FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5
FMOVdcc 10 ..... 110101 0 cond:4 1 cc:1 0 000010 ..... \
rd=%dfp_rd rs2=%dfp_rs2
FMOVqcc 10 ..... 110101 0 cond:4 1 cc:1 0 000011 ..... \
rd=%qfp_rd rs2=%qfp_rs2
FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5
FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5
FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5
FMOVdfcc 10 ..... 110101 0 cond:4 0 cc:2 000010 ..... \
rd=%dfp_rd rs2=%dfp_rs2
FMOVqfcc 10 ..... 110101 0 cond:4 0 cc:2 000011 ..... \
rd=%qfp_rd rs2=%qfp_rs2
FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5
FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5
FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5
FMOVRd 10 ..... 110101 rs1:5 0 cond:3 00110 ..... \
rd=%dfp_rd rs2=%dfp_rs2
FMOVRq 10 ..... 110101 rs1:5 0 cond:3 00111 ..... \
rd=%qfp_rd rs2=%qfp_rs2
FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5
FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5
FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5
FCMPd 10 000 cc:2 110101 ..... 0 0101 0010 ..... \
rs1=%dfp_rs1 rs2=%dfp_rs2
FCMPq 10 000 cc:2 110101 ..... 0 0101 0011 ..... \
rs1=%qfp_rs1 rs2=%qfp_rs2
FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5
FCMPEd 10 000 cc:2 110101 rs1:5 0 0101 0110 rs2:5
FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
FCMPEd 10 000 cc:2 110101 ..... 0 0101 0110 ..... \
rs1=%dfp_rs1 rs2=%dfp_rs2
FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
rs1=%qfp_rs1 rs2=%qfp_rs2
{
[
@ -323,93 +388,187 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r
ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r
ADDXC 10 ..... 110110 ..... 0 0001 0001 ..... @r_r_r
ADDXCcc 10 ..... 110110 ..... 0 0001 0011 ..... @r_r_r
UMULXHI 10 ..... 110110 ..... 0 0001 0110 ..... @r_r_r
LZCNT 10 ..... 110110 00000 0 0001 0111 ..... @r_r2
XMULX 10 ..... 110110 ..... 1 0001 0101 ..... @r_r_r
XMULXHI 10 ..... 110110 ..... 1 0001 0110 ..... @r_r_r
ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r
ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r
FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r
FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r
FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r
FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r
FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r
FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r
FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r
CMASK8 10 00000 110110 00000 0 0001 1011 rs2:5
CMASK16 10 00000 110110 00000 0 0001 1101 rs2:5
CMASK32 10 00000 110110 00000 0 0001 1111 rs2:5
FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r
FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r
FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r
FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @r_r_r
FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r
FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r
FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r
FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r
FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2
FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2
PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r
FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_d_d
FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_d_d
FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_d_d
FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_d_d
FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_d_d
FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_d_d
FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_d_d
FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_d_d
FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r
FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r
BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r
FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @r_r2
FSLL16 10 ..... 110110 ..... 0 0010 0001 ..... @d_d_d
FSRL16 10 ..... 110110 ..... 0 0010 0011 ..... @d_d_d
FSLAS16 10 ..... 110110 ..... 0 0010 1001 ..... @d_d_d
FSRA16 10 ..... 110110 ..... 0 0010 1011 ..... @d_d_d
FSLL32 10 ..... 110110 ..... 0 0010 0101 ..... @d_d_d
FSRL32 10 ..... 110110 ..... 0 0010 0111 ..... @d_d_d
FSLAS32 10 ..... 110110 ..... 0 0010 1101 ..... @d_d_d
FSRA32 10 ..... 110110 ..... 0 0010 1111 ..... @d_d_d
FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d
FPCMPULE8 10 ..... 110110 ..... 1 0010 0000 ..... @r_d_d
FPCMPUGT8 10 ..... 110110 ..... 1 0010 1000 ..... @r_d_d
FPCMPNE8 10 ..... 110110 ..... 1 0010 0010 ..... @r_d_d
FPCMPEQ8 10 ..... 110110 ..... 1 0010 1010 ..... @r_d_d
FPCMPLE8 10 ..... 110110 ..... 0 0011 0100 ..... @r_d_d
FPCMPGT8 10 ..... 110110 ..... 0 0011 1100 ..... @r_d_d
FPCMPULE16 10 ..... 110110 ..... 1 0010 1110 ..... @r_d_d
FPCMPUGT16 10 ..... 110110 ..... 1 0010 1011 ..... @r_d_d
FPCMPULE32 10 ..... 110110 ..... 1 0010 1111 ..... @r_d_d
FPCMPUGT32 10 ..... 110110 ..... 1 0010 1100 ..... @r_d_d
FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @d_r_d
FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @d_r_r
FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @d_r_r
FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @d_d_d
FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @d_d_d
FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @d_r_r
FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @d_r_r
FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @d_d_d
FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_d2
FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_d2
PDIST 10 ..... 110110 ..... 0 0011 1110 ..... \
&r_r_r_r rd=%dfp_rd rs1=%dfp_rd rs2=%dfp_rs1 rs3=%dfp_rs2
PDISTN 10 ..... 110110 ..... 0 0011 1111 ..... @r_d_d
FMEAN16 10 ..... 110110 ..... 0 0100 0000 ..... @d_d_d
SUBXC 10 ..... 110110 ..... 0 0100 0001 ..... @r_r_r
SUBXCcc 10 ..... 110110 ..... 0 0100 0011 ..... @r_r_r
FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d
FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d
FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r
BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @d_d_d
FEXPAND 10 ..... 110110 00000 0 0100 1101 ..... @d_r2
FALIGNDATAi 10 ..... 110110 ..... 0 0100 1001 ..... @d_r_d
FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @d_d1 # FSRC1d
FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s
FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d
FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @d_d2 # FSRC2d
FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s
FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d
FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @d_d1 # FNOT1d
FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s
FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d
FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @d_d2 # FNOT2d
FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s
FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @r_r_r
FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @d_d_d
FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r
FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @r_r_r
FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @d_d_d
FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r
FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @r_r_r
FPADD64 10 ..... 110110 ..... 0 0100 0010 ..... @d_d_d
FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @d_d_d
FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r
FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @r_r_r
FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @d_d_d
FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r
FPSUB64 10 ..... 110110 ..... 0 0100 0110 ..... @d_d_d
FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @r_r_r
FPADDS16 10 ..... 110110 ..... 0 0101 1000 ..... @d_d_d
FPADDS16s 10 ..... 110110 ..... 0 0101 1001 ..... @r_r_r
FPADDS32 10 ..... 110110 ..... 0 0101 1010 ..... @d_d_d
FPADDS32s 10 ..... 110110 ..... 0 0101 1011 ..... @r_r_r
FPSUBS16 10 ..... 110110 ..... 0 0101 1100 ..... @d_d_d
FPSUBS16s 10 ..... 110110 ..... 0 0101 1101 ..... @r_r_r
FPSUBS32 10 ..... 110110 ..... 0 0101 1110 ..... @d_d_d
FPSUBS32s 10 ..... 110110 ..... 0 0101 1111 ..... @r_r_r
FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d
FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r
FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @r_r_r # FANDNOT2d
FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @d_d_d # FANDNOT2d
FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s
FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @r_r_r_swap # ... 1d
FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @d_d_d_swap # ... 1d
FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s
FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @r_r_r
FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @d_d_d
FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r
FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @r_r_r
FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @d_d_d
FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r
FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @r_r_r
FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @d_d_d
FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r
FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @r_r_r
FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @d_d_d
FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r
FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @r_r_r # FORNOT2d
FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @d_d_d # FORNOT2d
FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s
FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @r_r_r_swap # ... 1d
FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @d_d_d_swap # ... 1d
FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s
FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r
FORd 10 ..... 110110 ..... 0 0111 1100 ..... @d_d_d
FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r
FZEROd 10 rd:5 110110 00000 0 0110 0000 00000
FZEROd 10 ..... 110110 00000 0 0110 0000 00000 rd=%dfp_rd
FZEROs 10 rd:5 110110 00000 0 0110 0001 00000
FONEd 10 rd:5 110110 00000 0 0111 1110 00000
FONEd 10 ..... 110110 00000 0 0111 1110 00000 rd=%dfp_rd
FONEs 10 rd:5 110110 00000 0 0111 1111 00000
MOVsTOuw 10 ..... 110110 00000 1 0001 0001 ..... @r_r2
MOVsTOsw 10 ..... 110110 00000 1 0001 0011 ..... @r_r2
MOVwTOs 10 ..... 110110 00000 1 0001 1001 ..... @r_r2
MOVdTOx 10 ..... 110110 00000 1 0001 0000 ..... @r_d2
MOVxTOd 10 ..... 110110 00000 1 0001 1000 ..... @d_r2
FPADD8 10 ..... 110110 ..... 1 0010 0100 ..... @d_d_d
FPADDS8 10 ..... 110110 ..... 1 0010 0110 ..... @d_d_d
FPADDUS8 10 ..... 110110 ..... 1 0010 0111 ..... @d_d_d
FPADDUS16 10 ..... 110110 ..... 1 0010 0011 ..... @d_d_d
FPSUB8 10 ..... 110110 ..... 1 0101 0100 ..... @d_d_d
FPSUBS8 10 ..... 110110 ..... 1 0101 0110 ..... @d_d_d
FPSUBUS8 10 ..... 110110 ..... 1 0101 0111 ..... @d_d_d
FPSUBUS16 10 ..... 110110 ..... 1 0101 0011 ..... @d_d_d
FPMIN8 10 ..... 110110 ..... 1 0001 1010 ..... @d_d_d
FPMIN16 10 ..... 110110 ..... 1 0001 1011 ..... @d_d_d
FPMIN32 10 ..... 110110 ..... 1 0001 1100 ..... @d_d_d
FPMINU8 10 ..... 110110 ..... 1 0101 1010 ..... @d_d_d
FPMINU16 10 ..... 110110 ..... 1 0101 1011 ..... @d_d_d
FPMINU32 10 ..... 110110 ..... 1 0101 1100 ..... @d_d_d
FPMAX8 10 ..... 110110 ..... 1 0001 1101 ..... @d_d_d
FPMAX16 10 ..... 110110 ..... 1 0001 1110 ..... @d_d_d
FPMAX32 10 ..... 110110 ..... 1 0001 1111 ..... @d_d_d
FPMAXU8 10 ..... 110110 ..... 1 0101 1101 ..... @d_d_d
FPMAXU16 10 ..... 110110 ..... 1 0101 1110 ..... @d_d_d
FPMAXU32 10 ..... 110110 ..... 1 0101 1111 ..... @d_d_d
FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5
FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \
rs1=%dfp_rs1 rs2=%dfp_rs2
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
}
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
{
[
FMADDs 10 ..... 110111 ..... ..... 0001 ..... @r_r_r_r
FMADDd 10 ..... 110111 ..... ..... 0010 ..... @d_d_d_d
FMSUBs 10 ..... 110111 ..... ..... 0101 ..... @r_r_r_r
FMSUBd 10 ..... 110111 ..... ..... 0110 ..... @d_d_d_d
FNMSUBs 10 ..... 110111 ..... ..... 1001 ..... @r_r_r_r
FNMSUBd 10 ..... 110111 ..... ..... 1010 ..... @d_d_d_d
FNMADDs 10 ..... 110111 ..... ..... 1101 ..... @r_r_r_r
FNMADDd 10 ..... 110111 ..... ..... 1110 ..... @d_d_d_d
FPMADDX 10 ..... 110111 ..... ..... 0000 ..... @d_d_d_d
FPMADDXHI 10 ..... 110111 ..... ..... 0100 ..... @d_d_d_d
]
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
}
##
## Major Opcode 11 -- load and store instructions
##
%dfp_rd 25:5 !function=extract_dfpreg
%qfp_rd 25:5 !function=extract_qfpreg
&r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool
@r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1
@d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \
@ -477,6 +636,7 @@ STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA
LDF 11 ..... 100000 ..... . ............. @r_r_ri_na
LDFSR 11 00000 100001 ..... . ............. @n_r_ri
LDXFSR 11 00001 100001 ..... . ............. @n_r_ri
LDXEFSR 11 00011 100001 ..... . ............. @n_r_ri
LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na
LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na

4
target/sparc/ldst_helper.c
View File

@ -1395,6 +1395,10 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case ASI_TWINX_PL: /* Primary, twinx, LE */
case ASI_TWINX_S: /* Secondary, twinx */
case ASI_TWINX_SL: /* Secondary, twinx, LE */
case ASI_MON_P:
case ASI_MON_S:
case ASI_MON_AIUP:
case ASI_MON_AIUS:
/* These are always handled inline. */
g_assert_not_reached();

942
target/sparc/translate.c
View File

File diff suppressed because it is too large Load Diff

392
target/sparc/vis_helper.c
View File

@ -20,26 +20,44 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "crypto/clmul.h"
/* This function uses non-native bit order */
#define GET_FIELD(X, FROM, TO) \
((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
/* This function uses the order in the manuals, i.e. bit 0 is 2^0 */
#define GET_FIELD_SP(X, FROM, TO) \
GET_FIELD(X, 63 - (TO), 63 - (FROM))
target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
target_ulong helper_array8(target_ulong rs1, target_ulong rs2)
{
return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
(GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
(GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
(GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
(GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
(GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
(((pixel_addr >> 55) & 1) << 4) |
(GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
GET_FIELD_SP(pixel_addr, 11, 12);
/*
* From Oracle SPARC Architecture 2015:
* Architecturally, an illegal R[rs2] value (>5) causes the array
* instructions to produce undefined results. For historic reference,
* past implementations of these instructions have ignored R[rs2]{63:3}
* and have treated R[rs2] values of 6 and 7 as if they were 5.
*/
target_ulong n = MIN(rs2 & 7, 5);
target_ulong x_int = (rs1 >> 11) & 0x7ff;
target_ulong y_int = (rs1 >> 33) & 0x7ff;
target_ulong z_int = rs1 >> 55;
target_ulong lower_x = x_int & 3;
target_ulong lower_y = y_int & 3;
target_ulong lower_z = z_int & 1;
target_ulong middle_x = (x_int >> 2) & 15;
target_ulong middle_y = (y_int >> 2) & 15;
target_ulong middle_z = (z_int >> 1) & 15;
target_ulong upper_x = (x_int >> 6) & ((1 << n) - 1);
target_ulong upper_y = (y_int >> 6) & ((1 << n) - 1);
target_ulong upper_z = z_int >> 5;
return (upper_z << (17 + 2 * n))
| (upper_y << (17 + n))
| (upper_x << 17)
| (middle_z << 13)
| (middle_y << 9)
| (middle_x << 5)
| (lower_z << 4)
| (lower_y << 2)
| lower_x;
}
#if HOST_BIG_ENDIAN
@ -48,6 +66,7 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
#define VIS_W64(n) w[3 - (n)]
#define VIS_SW64(n) sw[3 - (n)]
#define VIS_L64(n) l[1 - (n)]
#define VIS_SL64(n) sl[1 - (n)]
#define VIS_B32(n) b[3 - (n)]
#define VIS_W32(n) w[1 - (n)]
#else
@ -56,6 +75,7 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
#define VIS_W64(n) w[n]
#define VIS_SW64(n) sw[n]
#define VIS_L64(n) l[n]
#define VIS_SL64(n) sl[n]
#define VIS_B32(n) b[n]
#define VIS_W32(n) w[n]
#endif
@ -66,6 +86,7 @@ typedef union {
uint16_t w[4];
int16_t sw[4];
uint32_t l[2];
int32_t sl[2];
uint64_t ll;
float64 d;
} VIS64;
@ -157,10 +178,10 @@ uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t src2)
s.ll = src1;
d.ll = src2;
d.VIS_W64(0) = do_ms16b(s.VIS_B64(0), d.VIS_SW64(0));
d.VIS_W64(1) = do_ms16b(s.VIS_B64(2), d.VIS_SW64(1));
d.VIS_W64(2) = do_ms16b(s.VIS_B64(4), d.VIS_SW64(2));
d.VIS_W64(3) = do_ms16b(s.VIS_B64(6), d.VIS_SW64(3));
d.VIS_W64(0) = (s.VIS_B64(0) * d.VIS_SW64(0) + 0x8000) >> 16;
d.VIS_W64(1) = (s.VIS_B64(2) * d.VIS_SW64(1) + 0x8000) >> 16;
d.VIS_W64(2) = (s.VIS_B64(4) * d.VIS_SW64(2) + 0x8000) >> 16;
d.VIS_W64(3) = (s.VIS_B64(6) * d.VIS_SW64(3) + 0x8000) >> 16;
return d.ll;
}
@ -180,46 +201,171 @@ uint64_t helper_fexpand(uint32_t src2)
return d.ll;
}
#define VIS_CMPHELPER(name, F) \
uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
s.ll = src1; \
d.ll = src2; \
\
d.VIS_W64(0) = F(s.VIS_W64(0), d.VIS_W64(0)) ? 1 : 0; \
d.VIS_W64(0) |= F(s.VIS_W64(1), d.VIS_W64(1)) ? 2 : 0; \
d.VIS_W64(0) |= F(s.VIS_W64(2), d.VIS_W64(2)) ? 4 : 0; \
d.VIS_W64(0) |= F(s.VIS_W64(3), d.VIS_W64(3)) ? 8 : 0; \
d.VIS_W64(1) = d.VIS_W64(2) = d.VIS_W64(3) = 0; \
\
return d.ll; \
} \
\
uint64_t name##32(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
s.ll = src1; \
d.ll = src2; \
\
d.VIS_L64(0) = F(s.VIS_L64(0), d.VIS_L64(0)) ? 1 : 0; \
d.VIS_L64(0) |= F(s.VIS_L64(1), d.VIS_L64(1)) ? 2 : 0; \
d.VIS_L64(1) = 0; \
\
return d.ll; \
uint64_t helper_fcmpeq8(uint64_t src1, uint64_t src2)
{
uint64_t a = src1 ^ src2;
uint64_t m = 0x7f7f7f7f7f7f7f7fULL;
uint64_t c = ~(((a & m) + m) | a | m);
/* a.......b.......c.......d.......e.......f.......g.......h....... */
c |= c << 7;
/* ab......bc......cd......de......ef......fg......gh......h....... */
c |= c << 14;
/* abcd....bcde....cdef....defg....efgh....fgh.....gh......h....... */
c |= c << 28;
/* abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h....... */
return c >> 56;
}
uint64_t helper_fcmpne8(uint64_t src1, uint64_t src2)
{
return helper_fcmpeq8(src1, src2) ^ 0xff;
}
uint64_t helper_fcmple8(uint64_t src1, uint64_t src2)
{
VIS64 s1, s2;
uint64_t r = 0;
s1.ll = src1;
s2.ll = src2;
for (int i = 0; i < 8; ++i) {
r |= (s1.VIS_SB64(i) <= s2.VIS_SB64(i)) << i;
}
return r;
}
#define FCMPGT(a, b) ((a) > (b))
#define FCMPEQ(a, b) ((a) == (b))
#define FCMPLE(a, b) ((a) <= (b))
#define FCMPNE(a, b) ((a) != (b))
uint64_t helper_fcmpgt8(uint64_t src1, uint64_t src2)
{
return helper_fcmple8(src1, src2) ^ 0xff;
}
VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
VIS_CMPHELPER(helper_fcmple, FCMPLE)
VIS_CMPHELPER(helper_fcmpne, FCMPNE)
uint64_t helper_fcmpule8(uint64_t src1, uint64_t src2)
{
VIS64 s1, s2;
uint64_t r = 0;
s1.ll = src1;
s2.ll = src2;
for (int i = 0; i < 8; ++i) {
r |= (s1.VIS_B64(i) <= s2.VIS_B64(i)) << i;
}
return r;
}
uint64_t helper_fcmpugt8(uint64_t src1, uint64_t src2)
{
return helper_fcmpule8(src1, src2) ^ 0xff;
}
uint64_t helper_fcmpeq16(uint64_t src1, uint64_t src2)
{
uint64_t a = src1 ^ src2;
uint64_t m = 0x7fff7fff7fff7fffULL;
uint64_t c = ~(((a & m) + m) | a | m);
/* a...............b...............c...............d............... */
c |= c << 15;
/* ab..............bc..............cd..............d............... */
c |= c << 30;
/* abcd............bcd.............cd..............d............... */
return c >> 60;
}
uint64_t helper_fcmpne16(uint64_t src1, uint64_t src2)
{
return helper_fcmpeq16(src1, src2) ^ 0xf;
}
uint64_t helper_fcmple16(uint64_t src1, uint64_t src2)
{
VIS64 s1, s2;
uint64_t r = 0;
s1.ll = src1;
s2.ll = src2;
for (int i = 0; i < 4; ++i) {
r |= (s1.VIS_SW64(i) <= s2.VIS_SW64(i)) << i;
}
return r;
}
uint64_t helper_fcmpgt16(uint64_t src1, uint64_t src2)
{
return helper_fcmple16(src1, src2) ^ 0xf;
}
uint64_t helper_fcmpule16(uint64_t src1, uint64_t src2)
{
VIS64 s1, s2;
uint64_t r = 0;
s1.ll = src1;
s2.ll = src2;
for (int i = 0; i < 4; ++i) {
r |= (s1.VIS_W64(i) <= s2.VIS_W64(i)) << i;
}
return r;
}
uint64_t helper_fcmpugt16(uint64_t src1, uint64_t src2)
{
return helper_fcmpule16(src1, src2) ^ 0xf;
}
uint64_t helper_fcmpeq32(uint64_t src1, uint64_t src2)
{
uint64_t a = src1 ^ src2;
return ((uint32_t)a == 0) | (a >> 32 ? 0 : 2);
}
uint64_t helper_fcmpne32(uint64_t src1, uint64_t src2)
{
uint64_t a = src1 ^ src2;
return ((uint32_t)a != 0) | (a >> 32 ? 2 : 0);
}
uint64_t helper_fcmple32(uint64_t src1, uint64_t src2)
{
VIS64 s1, s2;
uint64_t r = 0;
s1.ll = src1;
s2.ll = src2;
for (int i = 0; i < 2; ++i) {
r |= (s1.VIS_SL64(i) <= s2.VIS_SL64(i)) << i;
}
return r;
}
uint64_t helper_fcmpgt32(uint64_t src1, uint64_t src2)
{
return helper_fcmple32(src1, src2) ^ 3;
}
uint64_t helper_fcmpule32(uint64_t src1, uint64_t src2)
{
VIS64 s1, s2;
uint64_t r = 0;
s1.ll = src1;
s2.ll = src2;
for (int i = 0; i < 2; ++i) {
r |= (s1.VIS_L64(i) <= s2.VIS_L64(i)) << i;
}
return r;
}
uint64_t helper_fcmpugt32(uint64_t src1, uint64_t src2)
{
return helper_fcmpule32(src1, src2) ^ 3;
}
uint64_t helper_pdist(uint64_t sum, uint64_t src1, uint64_t src2)
{
@ -334,3 +480,131 @@ uint64_t helper_bshuffle(uint64_t gsr, uint64_t src1, uint64_t src2)
return r.ll;
}
uint64_t helper_cmask8(uint64_t gsr, uint64_t src)
{
uint32_t mask = 0;
mask |= (src & 0x01 ? 0x00000007 : 0x0000000f);
mask |= (src & 0x02 ? 0x00000060 : 0x000000e0);
mask |= (src & 0x04 ? 0x00000500 : 0x00000d00);
mask |= (src & 0x08 ? 0x00004000 : 0x0000c000);
mask |= (src & 0x10 ? 0x00030000 : 0x000b0000);
mask |= (src & 0x20 ? 0x00200000 : 0x00a00000);
mask |= (src & 0x40 ? 0x01000000 : 0x09000000);
mask |= (src & 0x80 ? 0x00000000 : 0x80000000);
return deposit64(gsr, 32, 32, mask);
}
uint64_t helper_cmask16(uint64_t gsr, uint64_t src)
{
uint32_t mask = 0;
mask |= (src & 0x1 ? 0x00000067 : 0x000000ef);
mask |= (src & 0x2 ? 0x00004500 : 0x0000cd00);
mask |= (src & 0x4 ? 0x00230000 : 0x00ab0000);
mask |= (src & 0x8 ? 0x01000000 : 0x89000000);
return deposit64(gsr, 32, 32, mask);
}
uint64_t helper_cmask32(uint64_t gsr, uint64_t src)
{
uint32_t mask = 0;
mask |= (src & 0x1 ? 0x00004567 : 0x0000cdef);
mask |= (src & 0x2 ? 0x01230000 : 0x89ab0000);
return deposit64(gsr, 32, 32, mask);
}
static inline uint16_t do_fchksm16(uint16_t src1, uint16_t src2)
{
uint16_t a = src1 + src2;
uint16_t c = a < src1;
return a + c;
}
uint64_t helper_fchksm16(uint64_t src1, uint64_t src2)
{
VIS64 r, s1, s2;
s1.ll = src1;
s2.ll = src2;
r.ll = 0;
r.VIS_W64(0) = do_fchksm16(s1.VIS_W64(0), s2.VIS_W64(0));
r.VIS_W64(1) = do_fchksm16(s1.VIS_W64(1), s2.VIS_W64(1));
r.VIS_W64(2) = do_fchksm16(s1.VIS_W64(2), s2.VIS_W64(2));
r.VIS_W64(3) = do_fchksm16(s1.VIS_W64(3), s2.VIS_W64(3));
return r.ll;
}
static inline int16_t do_fmean16(int16_t src1, int16_t src2)
{
return (src1 + src2 + 1) / 2;
}
uint64_t helper_fmean16(uint64_t src1, uint64_t src2)
{
VIS64 r, s1, s2;
s1.ll = src1;
s2.ll = src2;
r.ll = 0;
r.VIS_SW64(0) = do_fmean16(s1.VIS_SW64(0), s2.VIS_SW64(0));
r.VIS_SW64(1) = do_fmean16(s1.VIS_SW64(1), s2.VIS_SW64(1));
r.VIS_SW64(2) = do_fmean16(s1.VIS_SW64(2), s2.VIS_SW64(2));
r.VIS_SW64(3) = do_fmean16(s1.VIS_SW64(3), s2.VIS_SW64(3));
return r.ll;
}
uint64_t helper_fslas16(uint64_t src1, uint64_t src2)
{
VIS64 r, s1, s2;
s1.ll = src1;
s2.ll = src2;
r.ll = 0;
for (int i = 0; i < 4; ++i) {
int t = s1.VIS_SW64(i) << (s2.VIS_W64(i) % 16);
t = MIN(t, INT16_MAX);
t = MAX(t, INT16_MIN);
r.VIS_SW64(i) = t;
}
return r.ll;
}
uint64_t helper_fslas32(uint64_t src1, uint64_t src2)
{
VIS64 r, s1, s2;
s1.ll = src1;
s2.ll = src2;
r.ll = 0;
for (int i = 0; i < 2; ++i) {
int64_t t = (int64_t)(int32_t)s1.VIS_L64(i) << (s2.VIS_L64(i) % 32);
t = MIN(t, INT32_MAX);
t = MAX(t, INT32_MIN);
r.VIS_L64(i) = t;
}
return r.ll;
}
uint64_t helper_xmulx(uint64_t src1, uint64_t src2)
{
return int128_getlo(clmul_64(src1, src2));
}
uint64_t helper_xmulxhi(uint64_t src1, uint64_t src2)
{
return int128_gethi(clmul_64(src1, src2));
}