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hw/mips/gt64xxx_pci: Fix 'braces' coding style issues 

Since we'll move this code around, fix its style first:

  ERROR: braces {} are necessary for all arms of this statement

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190624222844.26584-4-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2019-06-25 00:28:37 +02:00 committed by Aleksandar Markovic
parent 91ce82b2fe
commit 5353965544
1 changed files with 18 additions and 9 deletions
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27
hw/mips/gt64xxx_pci.c
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@ -257,19 +257,25 @@ static void check_reserved_space(hwaddr *start, hwaddr *length)
hwaddr begin = *start; hwaddr begin = *start;
hwaddr end = *start + *length; hwaddr end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL) if (end >= 0x1e000000LL && end < 0x1f100000LL) {
end = 0x1e000000LL; end = 0x1e000000LL;
if (begin >= 0x1e000000LL && begin < 0x1f100000LL) }
if (begin >= 0x1e000000LL && begin < 0x1f100000LL) {
begin = 0x1f100000LL; begin = 0x1f100000LL;
if (end >= 0x1fc00000LL && end < 0x1fd00000LL) }
if (end >= 0x1fc00000LL && end < 0x1fd00000LL) {
end = 0x1fc00000LL; end = 0x1fc00000LL;
if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) }
if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) {
begin = 0x1fd00000LL; begin = 0x1fd00000LL;
}
/* XXX: This is broken when a reserved range splits the requested range */ /* XXX: This is broken when a reserved range splits the requested range */
if (end >= 0x1f100000LL && begin < 0x1e000000LL) if (end >= 0x1f100000LL && begin < 0x1e000000LL) {
end = 0x1e000000LL; end = 0x1e000000LL;
if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) }
if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) {
end = 0x1fc00000LL; end = 0x1fc00000LL;
}
*start = begin; *start = begin;
*length = end - begin; *length = end - begin;
@ -385,8 +391,9 @@ static void gt64120_writel (void *opaque, hwaddr addr,
PCIHostState *phb = PCI_HOST_BRIDGE(s); PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t saddr; uint32_t saddr;
if (!(s->regs[GT_CPU] & 0x00001000)) if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val); val = bswap32(val);
}
saddr = (addr & 0xfff) >> 2; saddr = (addr & 0xfff) >> 2;
switch (saddr) { switch (saddr) {
@ -937,8 +944,9 @@ static uint64_t gt64120_readl (void *opaque,
break; break;
} }
if (!(s->regs[GT_CPU] & 0x00001000)) if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val); val = bswap32(val);
}
return val; return val;
} }
@ -990,8 +998,9 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
/* The pic level is the logical OR of all the PCI irqs mapped to it. */ /* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0; pic_level = 0;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
if (pic_irq == piix4_dev->config[0x60 + i]) if (pic_irq == piix4_dev->config[0x60 + i]) {
pic_level |= pci_irq_levels[i]; pic_level |= pci_irq_levels[i];
}
} }
qemu_set_irq(pic[pic_irq], pic_level); qemu_set_irq(pic[pic_irq], pic_level);
} }