mirror of https://github.com/xemu-project/xemu.git
target-arm queue:
* More MVE emulation work * Implement M-profile trapping on division by zero * kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() * hw/char/pl011: add support for sending break * fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices * hw/dma/pl330: Add memory region to replace default * sbsa-ref: Rename SBSA_GWDT enum value * fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices * docs: Document how to use gdb with unix sockets -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmEmHMoZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lttEACshvkatSTGXw2PzDNln2U7 lLLQslCRAkqLLaO9vDg9PQsbP+4bP7xSUHLPXdWD4a0tf7NCD7+Me3umJMoUj4cO WfDIhgNwMTfCz2XoFIuOyiqhl8DNOGL2lOBZqQhCacgTdeA6FdoEIUUggHW2JN2A Dzbx70nWuT7MF/w66OCH40dCUWdYZw40JmbQCCOzXWl46bwSjeTHH5pkHuhfWSzC cJS/qcFgmULFdKgSF1vmf5+2LDk/9CaOKE8T8jowkmKLO3g5pYjgGM+7adjVPbB4 9nizmgDx53sQN1WCt9SjP61tU9QmEtYgXag+Kd/E/4f9li5pauo2Tmfzdc5otF8S enHhzAy9wgAnmWv9Mc/0CpIulbwGlKP8ySWpeNpFeg2x+1tV4BeXYCWZXEzu9YBw RFTxGfCchnPq/SOFLULQxqmtSSHALSvhi/q7XU+6dmYLnvSHed8uoENFmvtA04zi Rc0MHHehnkImI8A6B+wUOCbkqDuWjGu10IzPjGt8Xm/D90/qkYKcpalU7gdu8ksY PBMqeC/R06cL7qj41LND+IHgzMUu31CB8g9aQ+PqP75wJ6mOH0p2lGCFv5toYrHS CI0z2sNafY8Jugdi6JQKeRVeneo7u/tlqkT3ofutp6Gk8GD14Pnv2DDWMcPF9hJS 4+fudn2L/53qi7OUgMqbjA== =u00S -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210825' into staging target-arm queue: * More MVE emulation work * Implement M-profile trapping on division by zero * kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() * hw/char/pl011: add support for sending break * fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices * hw/dma/pl330: Add memory region to replace default * sbsa-ref: Rename SBSA_GWDT enum value * fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices * docs: Document how to use gdb with unix sockets # gpg: Signature made Wed 25 Aug 2021 11:34:50 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210825: (44 commits) docs: Document how to use gdb with unix sockets fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices sbsa-ref: Rename SBSA_GWDT enum value hw/dma/pl330: Add memory region to replace default fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices hw/char/pl011: add support for sending break target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() target/arm: Implement M-profile trapping on division by zero target/arm: Re-indent sdiv and udiv helpers target/arm: Implement MVE interleaving loads/stores target/arm: Implement MVE scatter-gather immediate forms target/arm: Implement MVE scatter-gather insns target/arm: Implement MVE VCTP target/arm: Implement MVE VPNOT target/arm: Implement MVE VMOV to/from 2 general-purpose registers target/arm: Implement MVE VMAXA, VMINA target/arm: Implement MVE VQABS, VQNEG target/arm: Implement MVE saturating doubling multiply accumulates target/arm: Implement MVE VMLA target/arm: Implement MVE VMLADAV and VMLSLDAV ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
52fecb8669
|
|
@ -15,7 +15,8 @@ The ``-s`` option will make QEMU listen for an incoming connection
|
|||
from gdb on TCP port 1234, and ``-S`` will make QEMU not start the
|
||||
guest until you tell it to from gdb. (If you want to specify which
|
||||
TCP port to use or to use something other than TCP for the gdbstub
|
||||
connection, use the ``-gdb dev`` option instead of ``-s``.)
|
||||
connection, use the ``-gdb dev`` option instead of ``-s``. See
|
||||
`Using unix sockets`_ for an example.)
|
||||
|
||||
.. parsed-literal::
|
||||
|
||||
|
|
@ -100,6 +101,29 @@ not just those in the cluster you are currently working on::
|
|||
|
||||
(gdb) set schedule-multiple on
|
||||
|
||||
Using unix sockets
|
||||
==================
|
||||
|
||||
An alternate method for connecting gdb to the QEMU gdbstub is to use
|
||||
a unix socket (if supported by your operating system). This is useful when
|
||||
running several tests in parallel, or if you do not have a known free TCP
|
||||
port (e.g. when running automated tests).
|
||||
|
||||
First create a chardev with the appropriate options, then
|
||||
instruct the gdbserver to use that device:
|
||||
|
||||
.. parsed-literal::
|
||||
|
||||
|qemu_system| -chardev socket,path=/tmp/gdb-socket,server=on,wait=off,id=gdb0 -gdb chardev:gdb0 -S ...
|
||||
|
||||
Start gdb as before, but this time connect using the path to
|
||||
the socket::
|
||||
|
||||
(gdb) target remote /tmp/gdb-socket
|
||||
|
||||
Note that to use a unix socket for the connection you will need
|
||||
gdb version 9.0 or newer.
|
||||
|
||||
Advanced debugging options
|
||||
==========================
|
||||
|
||||
|
|
|
|||
|
|
@ -173,6 +173,9 @@ static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
|
|||
int i;
|
||||
|
||||
dev = qdev_new("pl330");
|
||||
object_property_set_link(OBJECT(dev), "memory",
|
||||
OBJECT(get_system_memory()),
|
||||
&error_fatal);
|
||||
qdev_prop_set_uint8(dev, "num_events", nevents);
|
||||
qdev_prop_set_uint8(dev, "num_chnls", 8);
|
||||
qdev_prop_set_uint8(dev, "num_periph_req", nreq);
|
||||
|
|
|
|||
|
|
@ -534,6 +534,13 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
|
|||
*/
|
||||
create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
|
||||
|
||||
/*
|
||||
* SAI (Audio SSI (Synchronous Serial Interface))
|
||||
*/
|
||||
create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
|
||||
create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
|
||||
create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
|
||||
|
||||
/*
|
||||
* PWM
|
||||
*/
|
||||
|
|
@ -542,6 +549,11 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
|
|||
create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
|
||||
create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
|
||||
|
||||
/*
|
||||
* Audio ASRC (asynchronous sample rate converter)
|
||||
*/
|
||||
create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
|
||||
|
||||
/*
|
||||
* CAN
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -467,6 +467,13 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
|
|||
create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
|
||||
create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
|
||||
|
||||
/*
|
||||
* SAI (Audio SSI (Synchronous Serial Interface))
|
||||
*/
|
||||
create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
|
||||
create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
|
||||
create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
|
||||
|
||||
/*
|
||||
* OCOTP
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ enum {
|
|||
SBSA_GIC_DIST,
|
||||
SBSA_GIC_REDIST,
|
||||
SBSA_SECURE_EC,
|
||||
SBSA_GWDT,
|
||||
SBSA_GWDT_WS0,
|
||||
SBSA_GWDT_REFRESH,
|
||||
SBSA_GWDT_CONTROL,
|
||||
SBSA_SMMU,
|
||||
|
|
@ -140,7 +140,7 @@ static const int sbsa_ref_irqmap[] = {
|
|||
[SBSA_AHCI] = 10,
|
||||
[SBSA_EHCI] = 11,
|
||||
[SBSA_SMMU] = 12, /* ... to 15 */
|
||||
[SBSA_GWDT] = 16,
|
||||
[SBSA_GWDT_WS0] = 16,
|
||||
};
|
||||
|
||||
static const char * const valid_cpus[] = {
|
||||
|
|
@ -481,7 +481,7 @@ static void create_wdt(const SBSAMachineState *sms)
|
|||
hwaddr cbase = sbsa_ref_memmap[SBSA_GWDT_CONTROL].base;
|
||||
DeviceState *dev = qdev_new(TYPE_WDT_SBSA);
|
||||
SysBusDevice *s = SYS_BUS_DEVICE(dev);
|
||||
int irq = sbsa_ref_irqmap[SBSA_GWDT];
|
||||
int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
|
||||
|
||||
sysbus_realize_and_unref(s, &error_fatal);
|
||||
sysbus_mmio_map(s, 0, rbase);
|
||||
|
|
|
|||
|
|
@ -312,6 +312,9 @@ static void zynq_init(MachineState *machine)
|
|||
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
|
||||
|
||||
dev = qdev_new("pl330");
|
||||
object_property_set_link(OBJECT(dev), "memory",
|
||||
OBJECT(address_space_mem),
|
||||
&error_fatal);
|
||||
qdev_prop_set_uint8(dev, "num_chnls", 8);
|
||||
qdev_prop_set_uint8(dev, "num_periph_req", 4);
|
||||
qdev_prop_set_uint8(dev, "num_events", 16);
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include "hw/qdev-properties-system.h"
|
||||
#include "migration/vmstate.h"
|
||||
#include "chardev/char-fe.h"
|
||||
#include "chardev/char-serial.h"
|
||||
#include "qemu/log.h"
|
||||
#include "qemu/module.h"
|
||||
#include "trace.h"
|
||||
|
|
@ -231,6 +232,11 @@ static void pl011_write(void *opaque, hwaddr offset,
|
|||
s->read_count = 0;
|
||||
s->read_pos = 0;
|
||||
}
|
||||
if ((s->lcr ^ value) & 0x1) {
|
||||
int break_enable = value & 0x1;
|
||||
qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
|
||||
&break_enable);
|
||||
}
|
||||
s->lcr = value;
|
||||
pl011_set_read_trigger(s);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -269,6 +269,9 @@ struct PL330State {
|
|||
uint8_t num_faulting;
|
||||
uint8_t periph_busy[PL330_PERIPH_NUM];
|
||||
|
||||
/* Memory region that DMA operation access */
|
||||
MemoryRegion *mem_mr;
|
||||
AddressSpace *mem_as;
|
||||
};
|
||||
|
||||
#define TYPE_PL330 "pl330"
|
||||
|
|
@ -1108,7 +1111,7 @@ static inline const PL330InsnDesc *pl330_fetch_insn(PL330Chan *ch)
|
|||
uint8_t opcode;
|
||||
int i;
|
||||
|
||||
dma_memory_read(&address_space_memory, ch->pc, &opcode, 1);
|
||||
dma_memory_read(ch->parent->mem_as, ch->pc, &opcode, 1);
|
||||
for (i = 0; insn_desc[i].size; i++) {
|
||||
if ((opcode & insn_desc[i].opmask) == insn_desc[i].opcode) {
|
||||
return &insn_desc[i];
|
||||
|
|
@ -1122,7 +1125,7 @@ static inline void pl330_exec_insn(PL330Chan *ch, const PL330InsnDesc *insn)
|
|||
uint8_t buf[PL330_INSN_MAXSIZE];
|
||||
|
||||
assert(insn->size <= PL330_INSN_MAXSIZE);
|
||||
dma_memory_read(&address_space_memory, ch->pc, buf, insn->size);
|
||||
dma_memory_read(ch->parent->mem_as, ch->pc, buf, insn->size);
|
||||
insn->exec(ch, buf[0], &buf[1], insn->size - 1);
|
||||
}
|
||||
|
||||
|
|
@ -1186,7 +1189,7 @@ static int pl330_exec_cycle(PL330Chan *channel)
|
|||
if (q != NULL && q->len <= pl330_fifo_num_free(&s->fifo)) {
|
||||
int len = q->len - (q->addr & (q->len - 1));
|
||||
|
||||
dma_memory_read(&address_space_memory, q->addr, buf, len);
|
||||
dma_memory_read(s->mem_as, q->addr, buf, len);
|
||||
trace_pl330_exec_cycle(q->addr, len);
|
||||
if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) {
|
||||
pl330_hexdump(buf, len);
|
||||
|
|
@ -1217,7 +1220,7 @@ static int pl330_exec_cycle(PL330Chan *channel)
|
|||
fifo_res = pl330_fifo_get(&s->fifo, buf, len, q->tag);
|
||||
}
|
||||
if (fifo_res == PL330_FIFO_OK || q->z) {
|
||||
dma_memory_write(&address_space_memory, q->addr, buf, len);
|
||||
dma_memory_write(s->mem_as, q->addr, buf, len);
|
||||
trace_pl330_exec_cycle(q->addr, len);
|
||||
if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) {
|
||||
pl330_hexdump(buf, len);
|
||||
|
|
@ -1562,6 +1565,18 @@ static void pl330_realize(DeviceState *dev, Error **errp)
|
|||
"dma", PL330_IOMEM_SIZE);
|
||||
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
|
||||
|
||||
if (!s->mem_mr) {
|
||||
error_setg(errp, "'memory' link is not set");
|
||||
return;
|
||||
} else if (s->mem_mr == get_system_memory()) {
|
||||
/* Avoid creating new AS for system memory. */
|
||||
s->mem_as = &address_space_memory;
|
||||
} else {
|
||||
s->mem_as = g_new0(AddressSpace, 1);
|
||||
address_space_init(s->mem_as, s->mem_mr,
|
||||
memory_region_name(s->mem_mr));
|
||||
}
|
||||
|
||||
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pl330_exec_cycle_timer, s);
|
||||
|
||||
s->cfg[0] = (s->mgr_ns_at_rst ? 0x4 : 0) |
|
||||
|
|
@ -1656,6 +1671,9 @@ static Property pl330_properties[] = {
|
|||
DEFINE_PROP_UINT8("rd_q_dep", PL330State, rd_q_dep, 16),
|
||||
DEFINE_PROP_UINT16("data_buffer_dep", PL330State, data_buffer_dep, 256),
|
||||
|
||||
DEFINE_PROP_LINK("memory", PL330State, mem_mr,
|
||||
TYPE_MEMORY_REGION, MemoryRegion *),
|
||||
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -174,6 +174,11 @@ enum FslIMX7MemoryMap {
|
|||
FSL_IMX7_UART6_ADDR = 0x30A80000,
|
||||
FSL_IMX7_UART7_ADDR = 0x30A90000,
|
||||
|
||||
FSL_IMX7_SAI1_ADDR = 0x308A0000,
|
||||
FSL_IMX7_SAI2_ADDR = 0x308B0000,
|
||||
FSL_IMX7_SAI3_ADDR = 0x308C0000,
|
||||
FSL_IMX7_SAIn_SIZE = 0x10000,
|
||||
|
||||
FSL_IMX7_ENET1_ADDR = 0x30BE0000,
|
||||
FSL_IMX7_ENET2_ADDR = 0x30BF0000,
|
||||
|
||||
|
|
|
|||
|
|
@ -1017,6 +1017,9 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
|||
i, v);
|
||||
}
|
||||
qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
|
||||
if (cpu_isar_feature(aa32_mve, cpu)) {
|
||||
qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@
|
|||
#define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
|
||||
#define EXCP_LSERR 21 /* v8M LSERR SecureFault */
|
||||
#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
|
||||
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
|
||||
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
|
||||
|
||||
#define ARMV7M_EXCP_RESET 1
|
||||
|
|
|
|||
|
|
@ -33,8 +33,105 @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32)
|
|||
DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vldrb_sg_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrb_sg_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrh_sg_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vldrb_sg_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrb_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrb_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrh_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrh_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrw_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrd_sg_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vstrb_sg_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrb_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrb_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrh_sg_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrh_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrw_sg_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrd_sg_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vldrh_sg_os_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vldrh_sg_os_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrh_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrw_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrd_sg_os_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vstrh_sg_os_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrh_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrw_sg_os_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrd_sg_os_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vldrw_sg_wb_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vldrd_sg_wb_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrw_sg_wb_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vstrd_sg_wb_ud, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vld20b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld20h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld20w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vld21b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld21h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld21w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vld40b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld40h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld40w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vld41b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld41h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld41w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vld42b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld42h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld42w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vld43b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld43h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vld43w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vst20b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst20h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst20w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vst21b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst21h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst21w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vst40b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst40h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst40w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vst41b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst41h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst41w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vst42b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst42h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst42w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vst43b, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst43h, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vst43w, TCG_CALL_NO_WG, void, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vdup, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vidupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_viduph, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vidupw, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_5(mve_viwdupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(mve_viwduph, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(mve_viwdupw, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_5(mve_vdwdupb, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(mve_vdwduph, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(mve_vdwdupw, TCG_CALL_NO_WG, i32, env, ptr, i32, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
|
@ -64,12 +161,53 @@ DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
|||
DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vqabsb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqabsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqabsw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vqnegb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqnegh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqnegw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxab, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxah, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxaw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vminab, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vminah, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vminaw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vmovnbb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vmovnbh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vmovntb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vmovnth, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovunbb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovunbh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovuntb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovunth, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovnbsb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovnbsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovntsb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovntsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovnbub, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovnbuh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovntub, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vqmovntuh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vand, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vbic, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vpsel, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_1(mve_vpnot, TCG_CALL_NO_WG, void, env)
|
||||
|
||||
DEF_HELPER_FLAGS_2(mve_vctp, TCG_CALL_NO_WG, void, env, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vaddw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
|
|
@ -145,6 +283,11 @@ DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
|||
DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vmullpbh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vmullpth, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vmullpbw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vmullptw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmulhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
|
||||
|
|
@ -328,6 +471,30 @@ DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i3
|
|||
DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vmlab, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlah, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlaw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vmlasb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlash, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlasw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmlahb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmlahh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmlahw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vqrdmlahb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrdmlahh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrdmlahw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmlashb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmlashh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqdmlashw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vqrdmlashb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrdmlashh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrdmlashw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
|
||||
|
|
@ -349,6 +516,23 @@ DEF_HELPER_FLAGS_4(mve_vrmlaldavhuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
|
|||
DEF_HELPER_FLAGS_4(mve_vrmlsldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
|
||||
DEF_HELPER_FLAGS_4(mve_vrmlsldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavsb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavsh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavsw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavub, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavuh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavuw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlsdavb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlsdavh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlsdavw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavsxb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavsxh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmladavsxw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlsdavxb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlsdavxh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vmlsdavxw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vaddvsb, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vaddvub, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
|
|
@ -356,9 +540,36 @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
|||
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxvsb, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxvub, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxavb, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxavh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vmaxavw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vminvsb, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminvub, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminavb, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminavh, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vminavw, TCG_CALL_NO_WG, i32, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
|
||||
DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vabavsb, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vabavsh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vabavsw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vabavub, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vabavuh, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vabavuw, TCG_CALL_NO_WG, i32, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
|
||||
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
|
||||
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
|
||||
|
|
@ -391,6 +602,14 @@ DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
|||
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vqrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vqrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vqrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
|
||||
|
|
@ -463,3 +682,67 @@ DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
|
|||
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpeqb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpeqh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpeqw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpneb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpneh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpnew, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpcsb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpcsh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpcsw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmphib, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmphih, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmphiw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgeb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgeh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgew, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpltb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmplth, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpltw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgtb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgth, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgtw, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpleb, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmplew, TCG_CALL_NO_WG, void, env, ptr, ptr)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpeq_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpne_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpne_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpne_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpcs_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmphi_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmphi_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmphi_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpge_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpge_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpge_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmplt_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmplt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmplt_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmpgt_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(mve_vcmple_scalarb, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(mve_vcmple_scalarw, TCG_CALL_NO_WG, void, env, ptr, i32)
|
||||
|
|
|
|||
|
|
@ -9345,6 +9345,18 @@ uint32_t HELPER(sxtb16)(uint32_t x)
|
|||
return res;
|
||||
}
|
||||
|
||||
static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra)
|
||||
{
|
||||
/*
|
||||
* Take a division-by-zero exception if necessary; otherwise return
|
||||
* to get the usual non-trapping division behaviour (result of 0)
|
||||
*/
|
||||
if (arm_feature(env, ARM_FEATURE_M)
|
||||
&& (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) {
|
||||
raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t HELPER(uxtb16)(uint32_t x)
|
||||
{
|
||||
uint32_t res;
|
||||
|
|
@ -9353,19 +9365,24 @@ uint32_t HELPER(uxtb16)(uint32_t x)
|
|||
return res;
|
||||
}
|
||||
|
||||
int32_t HELPER(sdiv)(int32_t num, int32_t den)
|
||||
int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den)
|
||||
{
|
||||
if (den == 0)
|
||||
return 0;
|
||||
if (num == INT_MIN && den == -1)
|
||||
return INT_MIN;
|
||||
if (den == 0) {
|
||||
handle_possible_div0_trap(env, GETPC());
|
||||
return 0;
|
||||
}
|
||||
if (num == INT_MIN && den == -1) {
|
||||
return INT_MIN;
|
||||
}
|
||||
return num / den;
|
||||
}
|
||||
|
||||
uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
|
||||
uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den)
|
||||
{
|
||||
if (den == 0)
|
||||
return 0;
|
||||
if (den == 0) {
|
||||
handle_possible_div0_trap(env, GETPC());
|
||||
return 0;
|
||||
}
|
||||
return num / den;
|
||||
}
|
||||
|
||||
|
|
@ -9564,6 +9581,7 @@ void arm_log_exception(int idx)
|
|||
[EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
|
||||
[EXCP_LSERR] = "v8M LSERR UsageFault",
|
||||
[EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
|
||||
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
|
||||
};
|
||||
|
||||
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32)
|
|||
DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
|
||||
DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32)
|
||||
DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_RWG, s32, env, s32, s32)
|
||||
DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_RWG, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
|
||||
#define PAS_OP(pfx) \
|
||||
|
|
|
|||
|
|
@ -998,7 +998,6 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
|
|||
hwaddr xlat, len, doorbell_gpa;
|
||||
MemoryRegionSection mrs;
|
||||
MemoryRegion *mr;
|
||||
int ret = 1;
|
||||
|
||||
if (as == &address_space_memory) {
|
||||
return 0;
|
||||
|
|
@ -1006,15 +1005,19 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
|
|||
|
||||
/* MSI doorbell address is translated by an IOMMU */
|
||||
|
||||
rcu_read_lock();
|
||||
RCU_READ_LOCK_GUARD();
|
||||
|
||||
mr = address_space_translate(as, address, &xlat, &len, true,
|
||||
MEMTXATTRS_UNSPECIFIED);
|
||||
|
||||
if (!mr) {
|
||||
goto unlock;
|
||||
return 1;
|
||||
}
|
||||
|
||||
mrs = memory_region_find(mr, xlat, 1);
|
||||
|
||||
if (!mrs.mr) {
|
||||
goto unlock;
|
||||
return 1;
|
||||
}
|
||||
|
||||
doorbell_gpa = mrs.offset_within_address_space;
|
||||
|
|
@ -1025,11 +1028,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
|
|||
|
||||
trace_kvm_arm_fixup_msi_route(address, doorbell_gpa);
|
||||
|
||||
ret = 0;
|
||||
|
||||
unlock:
|
||||
rcu_read_unlock();
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
|
||||
|
|
|
|||
|
|
@ -2252,6 +2252,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
|
|||
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
|
||||
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
|
||||
break;
|
||||
case EXCP_DIVBYZERO:
|
||||
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
|
||||
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_DIVBYZERO_MASK;
|
||||
break;
|
||||
case EXCP_SWI:
|
||||
/* The PC already points to the next instruction. */
|
||||
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);
|
||||
|
|
|
|||
|
|
@ -35,11 +35,35 @@
|
|||
&2scalar qd qn rm size
|
||||
&1imm qd imm cmode op
|
||||
&2shift qd qm shift size
|
||||
&vidup qd rn size imm
|
||||
&viwdup qd rn rm size imm
|
||||
&vcmp qm qn size mask
|
||||
&vcmp_scalar qn rm size mask
|
||||
&shl_scalar qda rm size
|
||||
&vmaxv qm rda size
|
||||
&vabav qn qm rda size
|
||||
&vldst_sg qd qm rn size msize os
|
||||
&vldst_sg_imm qd qm a w imm
|
||||
&vldst_il qd rn size pat w
|
||||
|
||||
# scatter-gather memory size is in bits 6:4
|
||||
%sg_msize 6:1 4:1
|
||||
|
||||
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
|
||||
# Note that both Rn and Qd are 3 bits only (no D bit)
|
||||
@vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr
|
||||
|
||||
@vldst_sg .... .... .... rn:4 .... ... size:2 ... ... os:1 &vldst_sg \
|
||||
qd=%qd qm=%qm msize=%sg_msize
|
||||
|
||||
# Qm is in the fields usually labeled Qn
|
||||
@vldst_sg_imm .... .... a:1 . w:1 . .... .... .... . imm:7 &vldst_sg_imm \
|
||||
qd=%qd qm=%qn
|
||||
|
||||
# Deinterleaving load/interleaving store
|
||||
@vldst_il .... .... .. w:1 . rn:4 .... ... size:2 pat:2 ..... &vldst_il \
|
||||
qd=%qd
|
||||
|
||||
@1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm
|
||||
@1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0
|
||||
@2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn
|
||||
|
|
@ -84,6 +108,16 @@
|
|||
@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
|
||||
size=2 shift=%rshift_i5
|
||||
|
||||
@shl_scalar .... .... .... size:2 .. .... .... .... rm:4 &shl_scalar qda=%qd
|
||||
|
||||
# Vector comparison; 4-bit Qm but 3-bit Qn
|
||||
%mask_22_13 22:1 13:3
|
||||
@vcmp .... .... .. size:2 qn:3 . .... .... .... .... &vcmp qm=%qm mask=%mask_22_13
|
||||
@vcmp_scalar .... .... .. size:2 qn:3 . .... .... .... rm:4 &vcmp_scalar \
|
||||
mask=%mask_22_13
|
||||
|
||||
@vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=%qm
|
||||
|
||||
# Vector loads and stores
|
||||
|
||||
# Widening loads and narrowing stores:
|
||||
|
|
@ -119,6 +153,26 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \
|
|||
VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \
|
||||
size=2 p=1
|
||||
|
||||
# gather loads/scatter stores
|
||||
VLDR_S_sg 111 0 1100 1 . 01 .... ... 0 111 . .... .... @vldst_sg
|
||||
VLDR_U_sg 111 1 1100 1 . 01 .... ... 0 111 . .... .... @vldst_sg
|
||||
VSTR_sg 111 0 1100 1 . 00 .... ... 0 111 . .... .... @vldst_sg
|
||||
|
||||
VLDRW_sg_imm 111 1 1101 ... 1 ... 0 ... 1 1110 .... .... @vldst_sg_imm
|
||||
VLDRD_sg_imm 111 1 1101 ... 1 ... 0 ... 1 1111 .... .... @vldst_sg_imm
|
||||
VSTRW_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1110 .... .... @vldst_sg_imm
|
||||
VSTRD_sg_imm 111 1 1101 ... 0 ... 0 ... 1 1111 .... .... @vldst_sg_imm
|
||||
|
||||
# deinterleaving loads/interleaving stores
|
||||
VLD2 1111 1100 1 .. 1 .... ... 1 111 .. .. 00000 @vldst_il
|
||||
VLD4 1111 1100 1 .. 1 .... ... 1 111 .. .. 00001 @vldst_il
|
||||
VST2 1111 1100 1 .. 0 .... ... 1 111 .. .. 00000 @vldst_il
|
||||
VST4 1111 1100 1 .. 0 .... ... 1 111 .. .. 00001 @vldst_il
|
||||
|
||||
# Moves between 2 32-bit vector lanes and 2 general purpose registers
|
||||
VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd
|
||||
VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd
|
||||
|
||||
# Vector 2-op
|
||||
VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
|
||||
VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
|
||||
|
|
@ -136,6 +190,11 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
|
|||
VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
|
||||
VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
|
||||
|
||||
VQMOVUNB 111 0 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op
|
||||
VQMOVN_BS 111 0 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op
|
||||
|
||||
VMAXA 111 0 1110 0 . 11 .. 11 ... 0 1110 1 0 . 0 ... 1 @1op
|
||||
|
||||
VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
|
||||
}
|
||||
|
||||
|
|
@ -143,6 +202,9 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
|
|||
VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
|
||||
VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
|
||||
|
||||
VMOVNB 111 1 1110 0 . 11 .. 01 ... 0 1110 1 0 . 0 ... 1 @1op
|
||||
VQMOVN_BU 111 1 1110 0 . 11 .. 11 ... 0 1110 0 0 . 0 ... 1 @1op
|
||||
|
||||
VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
|
||||
}
|
||||
|
||||
|
|
@ -150,6 +212,11 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
|
|||
VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
|
||||
VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
|
||||
|
||||
VQMOVUNT 111 0 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op
|
||||
VQMOVN_TS 111 0 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op
|
||||
|
||||
VMINA 111 0 1110 0 . 11 .. 11 ... 1 1110 1 0 . 0 ... 1 @1op
|
||||
|
||||
VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
|
||||
}
|
||||
|
||||
|
|
@ -157,6 +224,9 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
|
|||
VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
|
||||
VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
|
||||
|
||||
VMOVNT 111 1 1110 0 . 11 .. 01 ... 1 1110 1 0 . 0 ... 1 @1op
|
||||
VQMOVN_TU 111 1 1110 0 . 11 .. 11 ... 1 1110 0 0 . 0 ... 1 @1op
|
||||
|
||||
VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
|
||||
}
|
||||
|
||||
|
|
@ -173,10 +243,16 @@ VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op
|
|||
VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op
|
||||
VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op
|
||||
|
||||
VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op
|
||||
VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op
|
||||
VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op
|
||||
VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op
|
||||
{
|
||||
VMULLP_B 111 . 1110 0 . 11 ... 1 ... 0 1110 . 0 . 0 ... 0 @2op_sz28
|
||||
VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op
|
||||
VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op
|
||||
}
|
||||
{
|
||||
VMULLP_T 111 . 1110 0 . 11 ... 1 ... 1 1110 . 0 . 0 ... 0 @2op_sz28
|
||||
VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op
|
||||
VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op
|
||||
}
|
||||
|
||||
VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op
|
||||
VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op
|
||||
|
|
@ -244,6 +320,9 @@ VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op
|
|||
VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op
|
||||
VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op
|
||||
|
||||
VQABS 1111 1111 1 . 11 .. 00 ... 0 0111 01 . 0 ... 0 @1op
|
||||
VQNEG 1111 1111 1 . 11 .. 00 ... 0 0111 11 . 0 ... 0 @1op
|
||||
|
||||
&vdup qd rt size
|
||||
# Qd is in the fields usually named Qn
|
||||
@vdup .... .... . . .. ... . rt:4 .... . . . . .... qd=%qn &vdup
|
||||
|
|
@ -253,6 +332,29 @@ VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=0
|
|||
VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size=1
|
||||
VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2
|
||||
|
||||
# Incrementing and decrementing dup
|
||||
|
||||
# VIDUP, VDDUP format immediate: 1 << (immh:imml)
|
||||
%imm_vidup 7:1 0:1 !function=vidup_imm
|
||||
|
||||
# VIDUP, VDDUP registers: Rm bits [3:1] from insn, bit 0 is 1;
|
||||
# Rn bits [3:1] from insn, bit 0 is 0
|
||||
%vidup_rm 1:3 !function=times_2_plus_1
|
||||
%vidup_rn 17:3 !function=times_2
|
||||
|
||||
@vidup .... .... . . size:2 .... .... .... .... .... \
|
||||
qd=%qd imm=%imm_vidup rn=%vidup_rn &vidup
|
||||
@viwdup .... .... . . size:2 .... .... .... .... .... \
|
||||
qd=%qd imm=%imm_vidup rm=%vidup_rm rn=%vidup_rn &viwdup
|
||||
{
|
||||
VIDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 111 . @vidup
|
||||
VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup
|
||||
}
|
||||
{
|
||||
VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup
|
||||
VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup
|
||||
}
|
||||
|
||||
# multiply-add long dual accumulate
|
||||
# rdahi: bits [3:1] from insn, bit 0 is 1
|
||||
# rdalo: bits [3:1] from insn, bit 0 is 0
|
||||
|
|
@ -262,26 +364,76 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2
|
|||
%size_16 16:1 !function=plus_1
|
||||
|
||||
&vmlaldav rdahi rdalo size qn qm x a
|
||||
&vmladav rda size qn qm x a
|
||||
|
||||
@vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \
|
||||
@vmlaldav .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \
|
||||
qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav
|
||||
@vmlaldav_nosz .... .... . ... ... . ... . .... .... qm:3 . \
|
||||
@vmlaldav_nosz .... .... . ... ... . ... x:1 .... .. a:1 . qm:3 . \
|
||||
qn=%qn rdahi=%rdahi rdalo=%rdalo size=0 &vmlaldav
|
||||
VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav
|
||||
VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav
|
||||
@vmladav .... .... .... ... . ... x:1 .... . . a:1 . qm:3 . \
|
||||
qn=%qn rda=%rdalo size=%size_16 &vmladav
|
||||
@vmladav_nosz .... .... .... ... . ... x:1 .... . . a:1 . qm:3 . \
|
||||
qn=%qn rda=%rdalo size=0 &vmladav
|
||||
|
||||
VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav
|
||||
{
|
||||
VMLADAV_S 1110 1110 1111 ... . ... . 1110 . 0 . 0 ... 0 @vmladav
|
||||
VMLALDAV_S 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav
|
||||
}
|
||||
{
|
||||
VMLADAV_U 1111 1110 1111 ... . ... . 1110 . 0 . 0 ... 0 @vmladav
|
||||
VMLALDAV_U 1111 1110 1 ... ... . ... . 1110 . 0 . 0 ... 0 @vmlaldav
|
||||
}
|
||||
|
||||
VRMLALDAVH_S 1110 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_nosz
|
||||
VRMLALDAVH_U 1111 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_nosz
|
||||
{
|
||||
VMLSDAV 1110 1110 1111 ... . ... . 1110 . 0 . 0 ... 1 @vmladav
|
||||
VMLSLDAV 1110 1110 1 ... ... . ... . 1110 . 0 . 0 ... 1 @vmlaldav
|
||||
}
|
||||
|
||||
VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav_nosz
|
||||
{
|
||||
VMLSDAV 1111 1110 1111 ... 0 ... . 1110 . 0 . 0 ... 1 @vmladav_nosz
|
||||
VRMLSLDAVH 1111 1110 1 ... ... 0 ... . 1110 . 0 . 0 ... 1 @vmlaldav_nosz
|
||||
}
|
||||
|
||||
VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_nosz
|
||||
VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_nosz
|
||||
|
||||
{
|
||||
VMAXV_S 1110 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
|
||||
VMINV_S 1110 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
|
||||
VMAXAV 1110 1110 1110 .. 00 .... 1111 0 0 . 0 ... 0 @vmaxv
|
||||
VMINAV 1110 1110 1110 .. 00 .... 1111 1 0 . 0 ... 0 @vmaxv
|
||||
VMLADAV_S 1110 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_nosz
|
||||
VRMLALDAVH_S 1110 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_nosz
|
||||
}
|
||||
|
||||
{
|
||||
VMAXV_U 1111 1110 1110 .. 10 .... 1111 0 0 . 0 ... 0 @vmaxv
|
||||
VMINV_U 1111 1110 1110 .. 10 .... 1111 1 0 . 0 ... 0 @vmaxv
|
||||
VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 0 @vmladav_nosz
|
||||
VRMLALDAVH_U 1111 1110 1 ... ... 0 ... . 1111 . 0 . 0 ... 0 @vmlaldav_nosz
|
||||
}
|
||||
|
||||
# Scalar operations
|
||||
|
||||
VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar
|
||||
VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar
|
||||
VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
|
||||
|
||||
{
|
||||
VSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar
|
||||
VRSHL_S_scalar 1110 1110 0 . 11 .. 11 ... 1 1110 0110 .... @shl_scalar
|
||||
VQSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 1110 .... @shl_scalar
|
||||
VQRSHL_S_scalar 1110 1110 0 . 11 .. 11 ... 1 1110 1110 .... @shl_scalar
|
||||
VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
|
||||
}
|
||||
|
||||
{
|
||||
VSHL_U_scalar 1111 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar
|
||||
VRSHL_U_scalar 1111 1110 0 . 11 .. 11 ... 1 1110 0110 .... @shl_scalar
|
||||
VQSHL_U_scalar 1111 1110 0 . 11 .. 01 ... 1 1110 1110 .... @shl_scalar
|
||||
VQRSHL_U_scalar 1111 1110 0 . 11 .. 11 ... 1 1110 1110 .... @shl_scalar
|
||||
VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
|
||||
}
|
||||
|
||||
VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar
|
||||
VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar
|
||||
VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar
|
||||
|
|
@ -301,11 +453,18 @@ VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar
|
|||
size=%size_28
|
||||
}
|
||||
|
||||
VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
|
||||
|
||||
VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
|
||||
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
|
||||
|
||||
# The U bit (28) is don't-care because it does not affect the result
|
||||
VMLA 111- 1110 0 . .. ... 1 ... 0 1110 . 100 .... @2scalar
|
||||
VMLAS 111- 1110 0 . .. ... 1 ... 1 1110 . 100 .... @2scalar
|
||||
|
||||
VQRDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 100 .... @2scalar
|
||||
VQRDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 100 .... @2scalar
|
||||
VQDMLAH 1110 1110 0 . .. ... 0 ... 0 1110 . 110 .... @2scalar
|
||||
VQDMLASH 1110 1110 0 . .. ... 0 ... 1 1110 . 110 .... @2scalar
|
||||
|
||||
# Vector add across vector
|
||||
{
|
||||
VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
|
||||
|
|
@ -313,9 +472,10 @@ VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
|
|||
rdahi=%rdahi rdalo=%rdalo
|
||||
}
|
||||
|
||||
# Predicate operations
|
||||
%mask_22_13 22:1 13:3
|
||||
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
|
||||
@vabav .... .... .. size:2 .... rda:4 .... .... .... &vabav qn=%qn qm=%qm
|
||||
|
||||
VABAV_S 111 0 1110 10 .. ... 0 .... 1111 . 0 . 0 ... 1 @vabav
|
||||
VABAV_U 111 1 1110 10 .. ... 0 .... 1111 . 0 . 0 ... 1 @vabav
|
||||
|
||||
# Logical immediate operations (1 reg and modified-immediate)
|
||||
|
||||
|
|
@ -364,6 +524,8 @@ VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
|
|||
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
|
||||
|
||||
# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
|
||||
# Note that VMOVL is encoded as "VSHLL with a zero shift count"; we
|
||||
# implement it that way rather than special-casing it in the decode.
|
||||
VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
|
||||
VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
|
||||
|
||||
|
|
@ -425,3 +587,31 @@ VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
|
|||
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
|
||||
|
||||
VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
|
||||
|
||||
# Comparisons. We expand out the conditions which are split across
|
||||
# encodings T1, T2, T3 and the fc bits. These include VPT, which is
|
||||
# effectively "VCMP then VPST". A plain "VCMP" has a mask field of zero.
|
||||
VCMPEQ 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp
|
||||
VCMPNE 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp
|
||||
{
|
||||
VPSEL 1111 1110 0 . 11 ... 1 ... 0 1111 . 0 . 0 ... 1 @2op_nosz
|
||||
VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp
|
||||
VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp
|
||||
}
|
||||
VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp
|
||||
VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp
|
||||
VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp
|
||||
VCMPLE 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 1 @vcmp
|
||||
|
||||
{
|
||||
VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101
|
||||
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
|
||||
VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_scalar
|
||||
}
|
||||
VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 0 0 .... @vcmp_scalar
|
||||
VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_scalar
|
||||
VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_scalar
|
||||
VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 0 0 .... @vcmp_scalar
|
||||
VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_scalar
|
||||
VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_scalar
|
||||
VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_scalar
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -748,5 +748,6 @@ BL 1111 0. .......... 11.1 ............ @branch24
|
|||
# This is DLSTP
|
||||
DLS 1111 0 0000 0 size:2 rn:4 1110 0000 0000 0001
|
||||
}
|
||||
VCTP 1111 0 0000 0 size:2 rn:4 1110 1000 0000 0001
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,7 +48,9 @@ long neon_element_offset(int reg, int element, MemOp memop);
|
|||
void gen_rev16(TCGv_i32 dest, TCGv_i32 var);
|
||||
void clear_eci_state(DisasContext *s);
|
||||
bool mve_eci_check(DisasContext *s);
|
||||
void mve_update_eci(DisasContext *s);
|
||||
void mve_update_and_store_eci(DisasContext *s);
|
||||
bool mve_skip_vmov(DisasContext *s, int vn, int index, int size);
|
||||
|
||||
static inline TCGv_i32 load_cpu_offset(int offset)
|
||||
{
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -581,7 +581,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool mve_skip_vmov(DisasContext *s, int vn, int index, int size)
|
||||
bool mve_skip_vmov(DisasContext *s, int vn, int index, int size)
|
||||
{
|
||||
/*
|
||||
* In a CPU with MVE, the VMOV (vector lane to general-purpose register)
|
||||
|
|
|
|||
|
|
@ -7992,9 +7992,9 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u)
|
|||
t1 = load_reg(s, a->rn);
|
||||
t2 = load_reg(s, a->rm);
|
||||
if (u) {
|
||||
gen_helper_udiv(t1, t1, t2);
|
||||
gen_helper_udiv(t1, cpu_env, t1, t2);
|
||||
} else {
|
||||
gen_helper_sdiv(t1, t1, t2);
|
||||
gen_helper_sdiv(t1, cpu_env, t1, t2);
|
||||
}
|
||||
tcg_temp_free_i32(t2);
|
||||
store_reg(s, a->rd, t1);
|
||||
|
|
@ -8669,6 +8669,39 @@ static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool trans_VCTP(DisasContext *s, arg_VCTP *a)
|
||||
{
|
||||
/*
|
||||
* M-profile Create Vector Tail Predicate. This insn is itself
|
||||
* predicated and is subject to beatwise execution.
|
||||
*/
|
||||
TCGv_i32 rn_shifted, masklen;
|
||||
|
||||
if (!dc_isar_feature(aa32_mve, s) || a->rn == 13 || a->rn == 15) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (!mve_eci_check(s) || !vfp_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* We pre-calculate the mask length here to avoid having
|
||||
* to have multiple helpers specialized for size.
|
||||
* We pass the helper "rn <= (1 << (4 - size)) ? (rn << size) : 16".
|
||||
*/
|
||||
rn_shifted = tcg_temp_new_i32();
|
||||
masklen = load_reg(s, a->rn);
|
||||
tcg_gen_shli_i32(rn_shifted, masklen, a->size);
|
||||
tcg_gen_movcond_i32(TCG_COND_LEU, masklen,
|
||||
masklen, tcg_constant_i32(1 << (4 - a->size)),
|
||||
rn_shifted, tcg_constant_i32(16));
|
||||
gen_helper_mve_vctp(cpu_env, masklen);
|
||||
tcg_temp_free_i32(masklen);
|
||||
tcg_temp_free_i32(rn_shifted);
|
||||
mve_update_eci(s);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -2028,11 +2028,23 @@ static uint64_t expand_byte_to_half(uint64_t x)
|
|||
| ((x & 0xff000000) << 24);
|
||||
}
|
||||
|
||||
static uint64_t pmull_h(uint64_t op1, uint64_t op2)
|
||||
uint64_t pmull_w(uint64_t op1, uint64_t op2)
|
||||
{
|
||||
uint64_t result = 0;
|
||||
int i;
|
||||
for (i = 0; i < 16; ++i) {
|
||||
uint64_t mask = (op1 & 0x0000000100000001ull) * 0xffffffff;
|
||||
result ^= op2 & mask;
|
||||
op1 >>= 1;
|
||||
op2 <<= 1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
uint64_t pmull_h(uint64_t op1, uint64_t op2)
|
||||
{
|
||||
uint64_t result = 0;
|
||||
int i;
|
||||
for (i = 0; i < 8; ++i) {
|
||||
uint64_t mask = (op1 & 0x0001000100010001ull) * 0xffff;
|
||||
result ^= op2 & mask;
|
||||
|
|
|
|||
|
|
@ -206,4 +206,15 @@ int16_t do_sqrdmlah_h(int16_t, int16_t, int16_t, bool, bool, uint32_t *);
|
|||
int32_t do_sqrdmlah_s(int32_t, int32_t, int32_t, bool, bool, uint32_t *);
|
||||
int64_t do_sqrdmlah_d(int64_t, int64_t, int64_t, bool, bool);
|
||||
|
||||
/*
|
||||
* 8 x 8 -> 16 vector polynomial multiply where the inputs are
|
||||
* in the low 8 bits of each 16-bit element
|
||||
*/
|
||||
uint64_t pmull_h(uint64_t op1, uint64_t op2);
|
||||
/*
|
||||
* 16 x 16 -> 32 vector polynomial multiply where the inputs are
|
||||
* in the low 16 bits of each 32-bit element
|
||||
*/
|
||||
uint64_t pmull_w(uint64_t op1, uint64_t op2);
|
||||
|
||||
#endif /* TARGET_ARM_VEC_INTERNALS_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue