mirror of https://github.com/xemu-project/xemu.git
PPC: Fix TLB invalidation bug within the PPC interrupt handler.
Commit 41557447d3
also introduced a subtle TLB
flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR
bits at the start of the interrupt handler, the logic towards the end of the
handler to force a TLB flush if either one of these bits were set would never
be triggered.
This patch simply changes the IR/DR bit check in the TLB flush logic to use
the original MSR value (albeit with some interrupt-specific bits cleared) so
that the IR/DR bits are preserved at the point where the check takes place.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andreas Färber <afaerber@suse.de>
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@ -2960,7 +2960,7 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp)
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if (asrr1 != -1)
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env->spr[asrr1] = env->spr[srr1];
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/* If we disactivated any translation, flush TLBs */
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if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
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if (msr & ((1 << MSR_IR) | (1 << MSR_DR)))
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tlb_flush(env, 1);
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if (msr_ile) {
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