mirror of https://github.com/xemu-project/xemu.git
riscv/sifive_u: Fix up file ordering
Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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648db19685
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523e346467
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@ -312,7 +312,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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g_free(nodename);
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g_free(nodename);
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}
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}
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static void riscv_sifive_u_init(MachineState *machine)
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static void sifive_u_machine_init(MachineState *machine)
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{
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{
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const struct MemmapEntry *memmap = sifive_u_memmap;
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const struct MemmapEntry *memmap = sifive_u_memmap;
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SiFiveUState *s = RISCV_U_MACHINE(machine);
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SiFiveUState *s = RISCV_U_MACHINE(machine);
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@ -403,6 +403,59 @@ static void riscv_sifive_u_init(MachineState *machine)
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&address_space_memory);
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&address_space_memory);
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}
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}
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static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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return s->start_in_flash;
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}
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static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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s->start_in_flash = value;
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}
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static void sifive_u_machine_instance_init(Object *obj)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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s->start_in_flash = false;
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object_property_add_bool(obj, "start-in-flash", sifive_u_machine_get_start_in_flash,
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sifive_u_machine_set_start_in_flash, NULL);
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object_property_set_description(obj, "start-in-flash",
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"Set on to tell QEMU's ROM to jump to "
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"flash. Otherwise QEMU will jump to DRAM",
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NULL);
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}
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static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->init = sifive_u_machine_init;
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mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
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mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
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mc->default_cpus = mc->min_cpus;
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}
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static const TypeInfo sifive_u_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_u"),
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.parent = TYPE_MACHINE,
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.class_init = sifive_u_machine_class_init,
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.instance_init = sifive_u_machine_instance_init,
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.instance_size = sizeof(SiFiveUState),
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};
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static void sifive_u_machine_init_register_types(void)
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{
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type_register_static(&sifive_u_machine_typeinfo);
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}
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type_init(sifive_u_machine_init_register_types)
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static void riscv_sifive_u_soc_init(Object *obj)
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static void riscv_sifive_u_soc_init(Object *obj)
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{
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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MachineState *ms = MACHINE(qdev_get_machine());
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@ -443,33 +496,6 @@ static void riscv_sifive_u_soc_init(Object *obj)
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TYPE_CADENCE_GEM);
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TYPE_CADENCE_GEM);
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}
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}
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static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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return s->start_in_flash;
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}
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static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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s->start_in_flash = value;
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}
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static void riscv_sifive_u_machine_instance_init(Object *obj)
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{
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SiFiveUState *s = RISCV_U_MACHINE(obj);
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s->start_in_flash = false;
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object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash,
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sifive_u_set_start_in_flash, NULL);
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object_property_set_description(obj, "start-in-flash",
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"Set on to tell QEMU's ROM to jump to "
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"flash. Otherwise QEMU will jump to DRAM",
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NULL);
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}
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static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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{
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{
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MachineState *ms = MACHINE(qdev_get_machine());
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MachineState *ms = MACHINE(qdev_get_machine());
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@ -607,29 +633,3 @@ static void riscv_sifive_u_soc_register_types(void)
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}
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}
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type_init(riscv_sifive_u_soc_register_types)
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type_init(riscv_sifive_u_soc_register_types)
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static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive U SDK";
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mc->init = riscv_sifive_u_init;
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mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
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mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
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mc->default_cpus = mc->min_cpus;
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}
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static const TypeInfo riscv_sifive_u_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_u"),
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.parent = TYPE_MACHINE,
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.class_init = riscv_sifive_u_machine_class_init,
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.instance_init = riscv_sifive_u_machine_instance_init,
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.instance_size = sizeof(SiFiveUState),
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};
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static void riscv_sifive_u_machine_init_register_types(void)
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{
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type_register_static(&riscv_sifive_u_machine_typeinfo);
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}
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type_init(riscv_sifive_u_machine_init_register_types)
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