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target/ppc: Hoist dcbz_size out of dcbz_common 

The 970 logic does not apply to dcbzep, which is an e500 insn.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-07-01 18:17:50 -07:00
parent 73a93ae5f4
commit 521a80d895
1 changed files with 15 additions and 15 deletions
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30
target/ppc/mem_helper.c
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@ -271,22 +271,12 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
} }
static void dcbz_common(CPUPPCState *env, target_ulong addr, static void dcbz_common(CPUPPCState *env, target_ulong addr,
uint32_t opcode, int mmu_idx, uintptr_t retaddr) int dcbz_size, int mmu_idx, uintptr_t retaddr)
{ {
target_ulong mask, dcbz_size = env->dcache_line_size; target_ulong mask = ~(target_ulong)(dcbz_size - 1);
uint32_t i;
void *haddr; void *haddr;
#if defined(TARGET_PPC64)
/* Check for dcbz vs dcbzl on 970 */
if (env->excp_model == POWERPC_EXCP_970 &&
!(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
dcbz_size = 32;
}
#endif
/* Align address */ /* Align address */
mask = ~(dcbz_size - 1);
addr &= mask; addr &= mask;
/* Check reservation */ /* Check reservation */
@ -300,7 +290,7 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr,
memset(haddr, 0, dcbz_size); memset(haddr, 0, dcbz_size);
} else { } else {
/* Slow path */ /* Slow path */
for (i = 0; i < dcbz_size; i += 8) { for (int i = 0; i < dcbz_size; i += 8) {
cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr); cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr);
} }
} }
@ -308,12 +298,22 @@ static void dcbz_common(CPUPPCState *env, target_ulong addr,
void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode) void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
{ {
dcbz_common(env, addr, opcode, ppc_env_mmu_index(env, false), GETPC()); int dcbz_size = env->dcache_line_size;
#if defined(TARGET_PPC64)
/* Check for dcbz vs dcbzl on 970 */
if (env->excp_model == POWERPC_EXCP_970 &&
!(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
dcbz_size = 32;
}
#endif
dcbz_common(env, addr, dcbz_size, ppc_env_mmu_index(env, false), GETPC());
} }
void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode) void helper_dcbzep(CPUPPCState *env, target_ulong addr, uint32_t opcode)
{ {
dcbz_common(env, addr, opcode, PPC_TLB_EPID_STORE, GETPC()); dcbz_common(env, addr, env->dcache_line_size, PPC_TLB_EPID_STORE, GETPC());
} }
void helper_icbi(CPUPPCState *env, target_ulong addr) void helper_icbi(CPUPPCState *env, target_ulong addr)