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ppc 6.2 queue: 

* Hash64 MMU fix for FreeBSD installer
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Merge tag 'pull-ppc-20211129' of https://github.com/legoater/qemu into staging

ppc 6.2 queue:

* Hash64 MMU fix for FreeBSD installer

# gpg: Signature made Mon 29 Nov 2021 09:49:54 PM CET
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-ppc-20211129' of https://github.com/legoater/qemu:
  target/ppc: fix Hash64 MMU update of PTE bit R

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-11-29 21:56:06 +01:00
parent a0fd8a5492 7bf00dfb51
commit 50456a6794
4 changed files with 12 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
hw/ppc/spapr.c
View File

@ -1414,7 +1414,7 @@ void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
kvmppc_write_hpte(ptex, pte0, pte1);
} else {
if (pte0 & HPTE64_V_VALID) {
stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
stq_p(spapr->htab + offset + HPTE64_DW1, pte1);
/*
* When setting valid, we write PTE1 first. This ensures
* proper synchronization with the reading code in
@ -1430,7 +1430,7 @@ void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
* ppc_hash64_pteg_search()
*/
smp_wmb();
stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
stq_p(spapr->htab + offset + HPTE64_DW1, pte1);
}
}
}
@ -1438,7 +1438,7 @@ void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
uint64_t pte1)
{
hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C;
SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
if (!spapr->htab) {
@ -1454,7 +1454,7 @@ static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
uint64_t pte1)
{
hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R;
SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
if (!spapr->htab) {

2
hw/ppc/spapr_softmmu.c
View File

@ -426,7 +426,7 @@ static void new_hpte_store(void *htab, uint64_t pteg, int slot,
addr += slot * HASH_PTE_SIZE_64;
stq_p(addr, pte0);
stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
stq_p(addr + HPTE64_DW1, pte1);
}
static int rehash_hpte(PowerPCCPU *cpu,

4
target/ppc/mmu-hash64.c
View File

@ -786,7 +786,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t
static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
{
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 16;
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R;
if (cpu->vhyp) {
PPCVirtualHypervisorClass *vhc =
@ -803,7 +803,7 @@ static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
{
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 15;
hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C;
if (cpu->vhyp) {
PPCVirtualHypervisorClass *vhc =

5
target/ppc/mmu-hash64.h
View File

@ -97,6 +97,11 @@ void ppc_hash64_finalize(PowerPCCPU *cpu);
#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
/* PTE offsets */
#define HPTE64_DW1 (HASH_PTE_SIZE_64 / 2)
#define HPTE64_DW1_R (HPTE64_DW1 + 6)
#define HPTE64_DW1_C (HPTE64_DW1 + 7)
/* Format changes for ARCH v3 */
#define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
#define HPTE64_R_3_0_SSIZE_SHIFT 58