mirror of https://github.com/xemu-project/xemu.git
target/mips: Restrict mips_cpu_dump_state() to cpu.c
As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-7-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
830b87ea25
commit
4f14ce4bf4
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@ -145,6 +145,83 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
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#endif /* !CONFIG_USER_ONLY */
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static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
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{
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int i;
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int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
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#define printfpr(fp) \
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do { \
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if (is_fpu64) \
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qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
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" fd:%13g fs:%13g psu: %13g\n", \
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(fp)->w[FP_ENDIAN_IDX], (fp)->d, \
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(double)(fp)->fd, \
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(double)(fp)->fs[FP_ENDIAN_IDX], \
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(double)(fp)->fs[!FP_ENDIAN_IDX]); \
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else { \
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fpr_t tmp; \
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tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
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tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
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qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
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" fd:%13g fs:%13g psu:%13g\n", \
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tmp.w[FP_ENDIAN_IDX], tmp.d, \
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(double)tmp.fd, \
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(double)tmp.fs[FP_ENDIAN_IDX], \
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(double)tmp.fs[!FP_ENDIAN_IDX]); \
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} \
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} while (0)
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qemu_fprintf(f,
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"CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
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env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
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get_float_exception_flags(&env->active_fpu.fp_status));
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for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
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qemu_fprintf(f, "%3s: ", fregnames[i]);
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printfpr(&env->active_fpu.fpr[i]);
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}
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#undef printfpr
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}
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static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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int i;
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qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
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" LO=0x" TARGET_FMT_lx " ds %04x "
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TARGET_FMT_lx " " TARGET_FMT_ld "\n",
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env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
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env->hflags, env->btarget, env->bcond);
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for (i = 0; i < 32; i++) {
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if ((i & 3) == 0) {
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qemu_fprintf(f, "GPR%02d:", i);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx,
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regnames[i], env->active_tc.gpr[i]);
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if ((i & 3) == 3) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
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TARGET_FMT_lx "\n",
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env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
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qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
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PRIx64 "\n",
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env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
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qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
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env->CP0_Config2, env->CP0_Config3);
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qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
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env->CP0_Config4, env->CP0_Config5);
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if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
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fpu_dump_state(env, f, flags);
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}
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}
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static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_RESET] = "reset",
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[EXCP_SRESET] = "soft reset",
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@ -79,7 +79,6 @@ extern const int mips_defs_number;
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void mips_cpu_do_interrupt(CPUState *cpu);
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bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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@ -25586,83 +25586,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
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}
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static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags)
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{
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int i;
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int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
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#define printfpr(fp) \
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do { \
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if (is_fpu64) \
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qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
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" fd:%13g fs:%13g psu: %13g\n", \
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(fp)->w[FP_ENDIAN_IDX], (fp)->d, \
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(double)(fp)->fd, \
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(double)(fp)->fs[FP_ENDIAN_IDX], \
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(double)(fp)->fs[!FP_ENDIAN_IDX]); \
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else { \
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fpr_t tmp; \
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tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
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tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
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qemu_fprintf(f, "w:%08x d:%016" PRIx64 \
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" fd:%13g fs:%13g psu:%13g\n", \
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tmp.w[FP_ENDIAN_IDX], tmp.d, \
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(double)tmp.fd, \
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(double)tmp.fs[FP_ENDIAN_IDX], \
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(double)tmp.fs[!FP_ENDIAN_IDX]); \
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} \
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} while (0)
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qemu_fprintf(f,
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"CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n",
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env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64,
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get_float_exception_flags(&env->active_fpu.fp_status));
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for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
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qemu_fprintf(f, "%3s: ", fregnames[i]);
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printfpr(&env->active_fpu.fpr[i]);
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}
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#undef printfpr
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}
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void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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int i;
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qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
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" LO=0x" TARGET_FMT_lx " ds %04x "
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TARGET_FMT_lx " " TARGET_FMT_ld "\n",
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env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
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env->hflags, env->btarget, env->bcond);
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for (i = 0; i < 32; i++) {
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if ((i & 3) == 0) {
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qemu_fprintf(f, "GPR%02d:", i);
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}
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qemu_fprintf(f, " %s " TARGET_FMT_lx,
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regnames[i], env->active_tc.gpr[i]);
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if ((i & 3) == 3) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x"
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TARGET_FMT_lx "\n",
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env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
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qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016"
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PRIx64 "\n",
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env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
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qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
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env->CP0_Config2, env->CP0_Config3);
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qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
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env->CP0_Config4, env->CP0_Config5);
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if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) {
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fpu_dump_state(env, f, flags);
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}
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}
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void mips_tcg_init(void)
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{
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int i;
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