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target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill 

Rather than adjust env->hflags so that the value computed
by cpu_mmu_index() changes, compute the mmu_idx that we
want directly and pass it down.

Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-28 15:58:52 +10:00
parent 167d6cd0e8
commit 4e999bf419
2 changed files with 16 additions and 20 deletions
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4
target/mips/cpu.h
View File

@ -1242,12 +1242,14 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
* MMU modes definitions. We carefully match the indices with our * MMU modes definitions. We carefully match the indices with our
* hflags layout. * hflags layout.
*/ */
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 2 #define MMU_USER_IDX 2
#define MMU_ERL_IDX 3
static inline int hflags_mmu_index(uint32_t hflags) static inline int hflags_mmu_index(uint32_t hflags)
{ {
if (hflags & MIPS_HFLAG_ERL) { if (hflags & MIPS_HFLAG_ERL) {
return 3; /* ERL */ return MMU_ERL_IDX;
} else { } else {
return hflags & MIPS_HFLAG_KSU; return hflags & MIPS_HFLAG_KSU;
} }

32
target/mips/tcg/sysemu/tlb_helper.c
View File

@ -623,7 +623,7 @@ static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
int directory_index, bool *huge_page, bool *hgpg_directory_hit, int directory_index, bool *huge_page, bool *hgpg_directory_hit,
uint64_t *pw_entrylo0, uint64_t *pw_entrylo1, uint64_t *pw_entrylo0, uint64_t *pw_entrylo1,
unsigned directory_shift, unsigned leaf_shift) unsigned directory_shift, unsigned leaf_shift, int ptw_mmu_idx)
{ {
int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
@ -638,8 +638,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
uint64_t w = 0; uint64_t w = 0;
if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
cpu_mmu_index(env, false)) != ptw_mmu_idx) != TLBRET_MATCH) {
TLBRET_MATCH) {
/* wrong base address */ /* wrong base address */
return 0; return 0;
} }
@ -666,8 +665,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
*pw_entrylo0 = entry; *pw_entrylo0 = entry;
} }
if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD, if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD,
cpu_mmu_index(env, false)) != ptw_mmu_idx) != TLBRET_MATCH) {
TLBRET_MATCH) {
return 0; return 0;
} }
if (!get_pte(env, vaddr2, leafentry_size, &entry)) { if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
@ -690,7 +688,7 @@ static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
} }
static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
int mmu_idx) int ptw_mmu_idx)
{ {
int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F;
int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F;
@ -776,7 +774,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
vaddr |= goffset; vaddr |= goffset;
switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit, switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit,
&pw_entrylo0, &pw_entrylo1, &pw_entrylo0, &pw_entrylo1,
directory_shift, leaf_shift)) directory_shift, leaf_shift, ptw_mmu_idx))
{ {
case 0: case 0:
return false; return false;
@ -793,7 +791,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
vaddr |= uoffset; vaddr |= uoffset;
switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit, switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit,
&pw_entrylo0, &pw_entrylo1, &pw_entrylo0, &pw_entrylo1,
directory_shift, leaf_shift)) directory_shift, leaf_shift, ptw_mmu_idx))
{ {
case 0: case 0:
return false; return false;
@ -810,7 +808,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
vaddr |= moffset; vaddr |= moffset;
switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit, switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit,
&pw_entrylo0, &pw_entrylo1, &pw_entrylo0, &pw_entrylo1,
directory_shift, leaf_shift)) directory_shift, leaf_shift, ptw_mmu_idx))
{ {
case 0: case 0:
return false; return false;
@ -825,8 +823,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
/* Leaf Level Page Table - First half of PTE pair */ /* Leaf Level Page Table - First half of PTE pair */
vaddr |= ptoffset0; vaddr |= ptoffset0;
if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
cpu_mmu_index(env, false)) != ptw_mmu_idx) != TLBRET_MATCH) {
TLBRET_MATCH) {
return false; return false;
} }
if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
@ -838,8 +835,7 @@ static bool page_table_walk_refill(CPUMIPSState *env, vaddr address,
/* Leaf Level Page Table - Second half of PTE pair */ /* Leaf Level Page Table - Second half of PTE pair */
vaddr |= ptoffset1; vaddr |= ptoffset1;
if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD,
cpu_mmu_index(env, false)) != ptw_mmu_idx) != TLBRET_MATCH) {
TLBRET_MATCH) {
return false; return false;
} }
if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
@ -944,12 +940,10 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
* Memory reads during hardware page table walking are performed * Memory reads during hardware page table walking are performed
* as if they were kernel-mode load instructions. * as if they were kernel-mode load instructions.
*/ */
int mode = (env->hflags & MIPS_HFLAG_KSU); int ptw_mmu_idx = (env->hflags & MIPS_HFLAG_ERL ?
bool ret_walker; MMU_ERL_IDX : MMU_KERNEL_IDX);
env->hflags &= ~MIPS_HFLAG_KSU;
ret_walker = page_table_walk_refill(env, address, mmu_idx); if (page_table_walk_refill(env, address, ptw_mmu_idx)) {
env->hflags |= mode;
if (ret_walker) {
ret = get_physical_address(env, &physical, &prot, address, ret = get_physical_address(env, &physical, &prot, address,
access_type, mmu_idx); access_type, mmu_idx);
if (ret == TLBRET_MATCH) { if (ret == TLBRET_MATCH) {