From 4e245a9e263e6272c5a47a46c770f3c3965cdf21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Fri, 10 Jun 2022 13:55:17 -0300 Subject: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 57c108b8646 introduced gen_set_gpri(), which already contains a check for if the destination register is 'zero'. The check in auipc and lui are then redundant. This patch removes those checks. Signed-off-by: Víctor Colombo Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index f1342f30f8..c190a59f22 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -32,17 +32,13 @@ static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a) static bool trans_lui(DisasContext *ctx, arg_lui *a) { - if (a->rd != 0) { - gen_set_gpri(ctx, a->rd, a->imm); - } + gen_set_gpri(ctx, a->rd, a->imm); return true; } static bool trans_auipc(DisasContext *ctx, arg_auipc *a) { - if (a->rd != 0) { - gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); - } + gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); return true; }