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aspeed: Add memory property to Aspeed SoC 

Multi-SoC machines can use this property to specify a memory container
for each SoC. Single SoC machines will just specify get_system_memory().

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220624003701.1363500-3-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Peter Delevoryas 2022-06-30 09:21:13 +02:00 committed by Cédric Le Goater
parent e37976d733
commit 4dd9d55416
5 changed files with 16 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/arm/aspeed.c
View File

@ -329,6 +329,8 @@ static void aspeed_machine_init(MachineState *machine)
&error_abort); &error_abort);
object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
&error_abort); &error_abort);
object_property_set_link(OBJECT(&bmc->soc), "memory",
OBJECT(get_system_memory()), &error_abort);
object_property_set_link(OBJECT(&bmc->soc), "dram", object_property_set_link(OBJECT(&bmc->soc), "dram",
OBJECT(machine->ram), &error_abort); OBJECT(machine->ram), &error_abort);
if (machine->kernel_filename) { if (machine->kernel_filename) {
@ -1336,6 +1338,8 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk); qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
object_property_set_link(OBJECT(&bmc->soc), "memory",
OBJECT(get_system_memory()), &error_abort);
qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
amc->uart_default); amc->uart_default);
qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);

5
hw/arm/aspeed_ast10x0.c
View File

@ -148,7 +148,6 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
{ {
AspeedSoCState *s = ASPEED_SOC(dev_soc); AspeedSoCState *s = ASPEED_SOC(dev_soc);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
MemoryRegion *system_memory = get_system_memory();
DeviceState *armv7m; DeviceState *armv7m;
Error *err = NULL; Error *err = NULL;
int i; int i;
@ -172,7 +171,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&s->armv7m), "memory", object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(system_memory), &error_abort); OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
/* Internal SRAM */ /* Internal SRAM */
@ -181,7 +180,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
error_propagate(errp, err); error_propagate(errp, err);
return; return;
} }
memory_region_add_subregion(system_memory, memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM], sc->memmap[ASPEED_DEV_SRAM],
&s->sram); &s->sram);

4
hw/arm/aspeed_ast2600.c
View File

@ -291,7 +291,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000, object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
&error_abort); &error_abort);
object_property_set_link(OBJECT(&s->cpu[i]), "memory", object_property_set_link(OBJECT(&s->cpu[i]), "memory",
OBJECT(get_system_memory()), &error_abort); OBJECT(s->memory), &error_abort);
if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return; return;
@ -329,7 +329,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err); error_propagate(errp, err);
return; return;
} }
memory_region_add_subregion(get_system_memory(), memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM], &s->sram); sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* DPMCU */ /* DPMCU */

12
hw/arm/aspeed_soc.c
View File

@ -243,7 +243,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
/* CPU */ /* CPU */
for (i = 0; i < sc->num_cpus; i++) { for (i = 0; i < sc->num_cpus; i++) {
object_property_set_link(OBJECT(&s->cpu[i]), "memory", object_property_set_link(OBJECT(&s->cpu[i]), "memory",
OBJECT(get_system_memory()), &error_abort); OBJECT(s->memory), &error_abort);
if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return; return;
} }
@ -256,7 +256,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err); error_propagate(errp, err);
return; return;
} }
memory_region_add_subregion(get_system_memory(), memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM], &s->sram); sc->memmap[ASPEED_DEV_SRAM], &s->sram);
/* SCU */ /* SCU */
@ -456,6 +456,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
} }
static Property aspeed_soc_properties[] = { static Property aspeed_soc_properties[] = {
DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *), MemoryRegion *),
DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default, DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default,
@ -555,14 +557,14 @@ void aspeed_soc_uart_init(AspeedSoCState *s)
int i, uart; int i, uart;
/* Attach an 8250 to the IO space as our UART */ /* Attach an 8250 to the IO space as our UART */
serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, serial_mm_init(s->memory, sc->memmap[s->uart_default], 2,
aspeed_soc_get_irq(s, s->uart_default), 38400, aspeed_soc_get_irq(s, s->uart_default), 38400,
serial_hd(0), DEVICE_LITTLE_ENDIAN); serial_hd(0), DEVICE_LITTLE_ENDIAN);
for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) { for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
if (uart == s->uart_default) { if (uart == s->uart_default) {
uart++; uart++;
} }
serial_mm_init(get_system_memory(), sc->memmap[uart], 2, serial_mm_init(s->memory, sc->memmap[uart], 2,
aspeed_soc_get_irq(s, uart), 38400, aspeed_soc_get_irq(s, uart), 38400,
serial_hd(i), DEVICE_LITTLE_ENDIAN); serial_hd(i), DEVICE_LITTLE_ENDIAN);
} }
@ -604,7 +606,7 @@ bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000); sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
} }
memory_region_add_subregion(get_system_memory(), memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
return true; return true;
} }

1
include/hw/arm/aspeed_soc.h
View File

@ -49,6 +49,7 @@ struct AspeedSoCState {
ARMCPU cpu[ASPEED_CPUS_NUM]; ARMCPU cpu[ASPEED_CPUS_NUM];
A15MPPrivState a7mpcore; A15MPPrivState a7mpcore;
ARMv7MState armv7m; ARMv7MState armv7m;
MemoryRegion *memory;
MemoryRegion *dram_mr; MemoryRegion *dram_mr;
MemoryRegion dram_container; MemoryRegion dram_container;
MemoryRegion sram; MemoryRegion sram;