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target-arm: Convert TLS registers 

Convert TLS registers to the new cp15 framework

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-06-20 11:57:11 +00:00
parent 7d57f40877
commit 4d31c59679
2 changed files with 19 additions and 58 deletions
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19
target-arm/helper.c
View File

@ -154,6 +154,22 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] = {
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
static const ARMCPRegInfo v6k_cp_reginfo[] = {
{ .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL0_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
.resetvalue = 0 },
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
.access = PL0_R|PL1_W,
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
.resetvalue = 0 },
{ .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
.resetvalue = 0 },
REGINFO_SENTINEL
};
void register_cp_regs_for_features(ARMCPU *cpu) void register_cp_regs_for_features(ARMCPU *cpu)
{ {
/* Register all the coprocessor registers based on feature bits */ /* Register all the coprocessor registers based on feature bits */
@ -169,6 +185,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} else { } else {
define_arm_cp_regs(cpu, not_v6_cp_reginfo); define_arm_cp_regs(cpu, not_v6_cp_reginfo);
} }
if (arm_feature(env, ARM_FEATURE_V6K)) {
define_arm_cp_regs(cpu, v6k_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V7)) { if (arm_feature(env, ARM_FEATURE_V7)) {
define_arm_cp_regs(cpu, v7_cp_reginfo); define_arm_cp_regs(cpu, v7_cp_reginfo);
} else { } else {

58
target-arm/translate.c
View File

@ -2460,64 +2460,9 @@ static int cp15_user_ok(CPUARMState *env, uint32_t insn)
} }
return 0; return 0;
} }
if (cpn == 13 && cpm == 0) {
/* TLS register. */
if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
return 1;
}
return 0; return 0;
} }
static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd)
{
TCGv tmp;
int cpn = (insn >> 16) & 0xf;
int cpm = insn & 0xf;
int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
if (!arm_feature(env, ARM_FEATURE_V6K))
return 0;
if (!(cpn == 13 && cpm == 0))
return 0;
if (insn & ARM_CP_RW_BIT) {
switch (op) {
case 2:
tmp = load_cpu_field(cp15.c13_tls1);
break;
case 3:
tmp = load_cpu_field(cp15.c13_tls2);
break;
case 4:
tmp = load_cpu_field(cp15.c13_tls3);
break;
default:
return 0;
}
store_reg(s, rd, tmp);
} else {
tmp = load_reg(s, rd);
switch (op) {
case 2:
store_cpu_field(tmp, cp15.c13_tls1);
break;
case 3:
store_cpu_field(tmp, cp15.c13_tls2);
break;
case 4:
store_cpu_field(tmp, cp15.c13_tls3);
break;
default:
tcg_temp_free_i32(tmp);
return 0;
}
}
return 1;
}
/* Disassemble system coprocessor (cp15) instruction. Return nonzero if /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
instruction is not defined. */ instruction is not defined. */
static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
@ -2548,9 +2493,6 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
rd = (insn >> 12) & 0xf; rd = (insn >> 12) & 0xf;
if (cp15_tls_load_store(env, s, insn, rd))
return 0;
tmp2 = tcg_const_i32(insn); tmp2 = tcg_const_i32(insn);
if (insn & ARM_CP_RW_BIT) { if (insn & ARM_CP_RW_BIT) {
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();