mirror of https://github.com/xemu-project/xemu.git
tests/qtest: Add STM32L4x5 EXTI QTest testcase
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240109160658.311932-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Inès Varhol
Peter Maydell
parent
52671f69f7
commit
4cb445717e
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@ -195,6 +195,10 @@ qtests_aspeed = \
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['aspeed_hace-test',
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'aspeed_smc-test',
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'aspeed_gpio-test']
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qtests_stm32l4x5 = \
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['stm32l4x5_exti-test']
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qtests_arm = \
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(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
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(config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
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@ -208,6 +212,7 @@ qtests_arm = \
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(config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
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(config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
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(config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
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(config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
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['arm-cpu-features',
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'boot-serial-test']
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@ -0,0 +1,524 @@
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/*
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* QTest testcase for STM32L4x5_EXTI
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*
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* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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#define EXTI_BASE_ADDR 0x40010400
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#define EXTI_IMR1 0x00
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#define EXTI_EMR1 0x04
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#define EXTI_RTSR1 0x08
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#define EXTI_FTSR1 0x0C
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#define EXTI_SWIER1 0x10
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#define EXTI_PR1 0x14
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#define EXTI_IMR2 0x20
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#define EXTI_EMR2 0x24
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#define EXTI_RTSR2 0x28
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#define EXTI_FTSR2 0x2C
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#define EXTI_SWIER2 0x30
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#define EXTI_PR2 0x34
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#define NVIC_ISER 0xE000E100
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#define NVIC_ISPR 0xE000E200
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#define NVIC_ICPR 0xE000E280
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#define EXTI0_IRQ 6
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#define EXTI1_IRQ 7
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#define EXTI35_IRQ 1
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static void enable_nvic_irq(unsigned int n)
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{
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writel(NVIC_ISER, 1 << n);
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}
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static void unpend_nvic_irq(unsigned int n)
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{
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writel(NVIC_ICPR, 1 << n);
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}
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static bool check_nvic_pending(unsigned int n)
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{
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return readl(NVIC_ISPR) & (1 << n);
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}
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static void exti_writel(unsigned int offset, uint32_t value)
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{
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writel(EXTI_BASE_ADDR + offset, value);
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}
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static uint32_t exti_readl(unsigned int offset)
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{
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return readl(EXTI_BASE_ADDR + offset);
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}
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static void exti_set_irq(int num, int level)
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{
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qtest_set_irq_in(global_qtest, "/machine/soc/exti", NULL,
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num, level);
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}
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static void test_reg_write_read(void)
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{
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/* Test that non-reserved bits in xMR and xTSR can be set and cleared */
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exti_writel(EXTI_IMR1, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_IMR1), ==, 0xFFFFFFFF);
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exti_writel(EXTI_IMR1, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_IMR1), ==, 0x00000000);
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exti_writel(EXTI_EMR1, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_EMR1), ==, 0xFFFFFFFF);
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exti_writel(EXTI_EMR1, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_EMR1), ==, 0x00000000);
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exti_writel(EXTI_RTSR1, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x007DFFFF);
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exti_writel(EXTI_RTSR1, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x00000000);
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exti_writel(EXTI_FTSR1, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x007DFFFF);
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exti_writel(EXTI_FTSR1, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x00000000);
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exti_writel(EXTI_IMR2, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x000000FF);
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exti_writel(EXTI_IMR2, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x00000000);
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exti_writel(EXTI_EMR2, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x000000FF);
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exti_writel(EXTI_EMR2, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x00000000);
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exti_writel(EXTI_RTSR2, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000078);
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exti_writel(EXTI_RTSR2, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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exti_writel(EXTI_FTSR2, 0xFFFFFFFF);
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g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000078);
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exti_writel(EXTI_FTSR2, 0x00000000);
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g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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}
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static void test_direct_lines_write(void)
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{
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/* Test that direct lines reserved bits are not written to */
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exti_writel(EXTI_RTSR1, 0xFF820000);
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g_assert_cmpuint(exti_readl(EXTI_RTSR1), ==, 0x00000000);
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exti_writel(EXTI_FTSR1, 0xFF820000);
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g_assert_cmpuint(exti_readl(EXTI_FTSR1), ==, 0x00000000);
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exti_writel(EXTI_SWIER1, 0xFF820000);
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g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000000);
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exti_writel(EXTI_PR1, 0xFF820000);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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exti_writel(EXTI_RTSR2, 0x00000087);
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g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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exti_writel(EXTI_FTSR2, 0x00000087);
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g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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exti_writel(EXTI_SWIER2, 0x00000087);
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g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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exti_writel(EXTI_PR2, 0x00000087);
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g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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}
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static void test_reserved_bits_write(void)
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{
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/* Test that reserved bits stay are not written to */
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exti_writel(EXTI_IMR2, 0xFFFFFF00);
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g_assert_cmpuint(exti_readl(EXTI_IMR2), ==, 0x00000000);
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exti_writel(EXTI_EMR2, 0xFFFFFF00);
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g_assert_cmpuint(exti_readl(EXTI_EMR2), ==, 0x00000000);
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exti_writel(EXTI_RTSR2, 0xFFFFFF00);
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g_assert_cmpuint(exti_readl(EXTI_RTSR2), ==, 0x00000000);
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exti_writel(EXTI_FTSR2, 0xFFFFFF00);
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g_assert_cmpuint(exti_readl(EXTI_FTSR2), ==, 0x00000000);
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exti_writel(EXTI_SWIER2, 0xFFFFFF00);
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g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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exti_writel(EXTI_PR2, 0xFFFFFF00);
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g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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}
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static void test_software_interrupt(void)
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{
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/*
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* Test that we can launch a software irq by :
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* - enabling its line in IMR
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* - and then setting a bit from '0' to '1' in SWIER
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*
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* And that the interruption stays pending in NVIC
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* even after clearing the pending bit in PR.
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*/
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/*
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* Testing interrupt line EXTI0
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* Bit 0 in EXTI_*1 registers (EXTI0) corresponds to GPIO Px_0
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*/
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enable_nvic_irq(EXTI0_IRQ);
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/* Check that there are no interrupts already pending in PR */
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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/* Check that this specific interrupt isn't pending in NVIC */
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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/* Enable interrupt line EXTI0 */
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exti_writel(EXTI_IMR1, 0x00000001);
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/* Set the right SWIER bit from '0' to '1' */
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exti_writel(EXTI_SWIER1, 0x00000000);
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exti_writel(EXTI_SWIER1, 0x00000001);
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/* Check that the write in SWIER was effective */
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g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000001);
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/* Check that the corresponding pending bit in PR is set */
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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/* Check that the corresponding interrupt is pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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/* Clear the pending bit in PR */
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exti_writel(EXTI_PR1, 0x00000001);
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/* Check that the write in PR was effective */
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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/* Check that the corresponding bit in SWIER was cleared */
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g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000000);
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/* Check that the interrupt is still pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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/*
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* Testing interrupt line EXTI35
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* Bit 3 in EXTI_*2 registers (EXTI35) corresponds to PVM 1 Wakeup
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*/
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enable_nvic_irq(EXTI35_IRQ);
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/* Check that there are no interrupts already pending */
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g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI35_IRQ));
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/* Enable interrupt line EXTI0 */
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exti_writel(EXTI_IMR2, 0x00000008);
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/* Set the right SWIER bit from '0' to '1' */
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exti_writel(EXTI_SWIER2, 0x00000000);
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exti_writel(EXTI_SWIER2, 0x00000008);
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/* Check that the write in SWIER was effective */
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g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000008);
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/* Check that the corresponding pending bit in PR is set */
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g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000008);
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/* Check that the corresponding interrupt is pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI35_IRQ));
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/* Clear the pending bit in PR */
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exti_writel(EXTI_PR2, 0x00000008);
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/* Check that the write in PR was effective */
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g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
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/* Check that the corresponding bit in SWIER was cleared */
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g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000000);
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/* Check that the interrupt is still pending in the NVIC */
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g_assert_true(check_nvic_pending(EXTI35_IRQ));
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/* Clean NVIC */
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unpend_nvic_irq(EXTI0_IRQ);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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unpend_nvic_irq(EXTI35_IRQ);
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g_assert_false(check_nvic_pending(EXTI35_IRQ));
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}
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static void test_edge_selector(void)
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{
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enable_nvic_irq(EXTI0_IRQ);
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/* Configure EXTI line 0 irq on rising edge */
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exti_set_irq(0, 1);
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exti_writel(EXTI_IMR1, 0x00000001);
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exti_writel(EXTI_RTSR1, 0x00000001);
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exti_writel(EXTI_FTSR1, 0x00000000);
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/* Test that an irq is raised on rising edge only */
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exti_set_irq(0, 0);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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exti_set_irq(0, 1);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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/* Clean the test */
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exti_writel(EXTI_PR1, 0x00000001);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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unpend_nvic_irq(EXTI0_IRQ);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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/* Configure EXTI line 0 irq on falling edge */
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exti_set_irq(0, 0);
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exti_writel(EXTI_IMR1, 0x00000001);
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exti_writel(EXTI_RTSR1, 0x00000000);
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exti_writel(EXTI_FTSR1, 0x00000001);
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/* Test that an irq is raised on falling edge only */
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exti_set_irq(0, 1);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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exti_set_irq(0, 0);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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/* Clean the test */
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exti_writel(EXTI_PR1, 0x00000001);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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unpend_nvic_irq(EXTI0_IRQ);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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/* Configure EXTI line 0 irq on falling and rising edge */
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exti_writel(EXTI_IMR1, 0x00000001);
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exti_writel(EXTI_RTSR1, 0x00000001);
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exti_writel(EXTI_FTSR1, 0x00000001);
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/* Test that an irq is raised on rising edge */
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exti_set_irq(0, 1);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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/* Clean the test */
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exti_writel(EXTI_PR1, 0x00000001);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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unpend_nvic_irq(EXTI0_IRQ);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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/* Test that an irq is raised on falling edge */
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exti_set_irq(0, 0);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000001);
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g_assert_true(check_nvic_pending(EXTI0_IRQ));
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/* Clean the test */
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exti_writel(EXTI_PR1, 0x00000001);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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unpend_nvic_irq(EXTI0_IRQ);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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/* Configure EXTI line 0 irq without selecting an edge trigger */
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exti_writel(EXTI_IMR1, 0x00000001);
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exti_writel(EXTI_RTSR1, 0x00000000);
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exti_writel(EXTI_FTSR1, 0x00000000);
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/* Test that no irq is raised */
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exti_set_irq(0, 1);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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exti_set_irq(0, 0);
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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}
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static void test_no_software_interrupt(void)
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{
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/*
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* Test that software irq doesn't happen when :
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* - corresponding bit in IMR isn't set
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* - SWIER is set to 1 before IMR is set to 1
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*/
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/*
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* Testing interrupt line EXTI0
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* Bit 0 in EXTI_*1 registers (EXTI0) corresponds to GPIO Px_0
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*/
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enable_nvic_irq(EXTI0_IRQ);
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/* Check that there are no interrupts already pending in PR */
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g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
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/* Check that this specific interrupt isn't pending in NVIC */
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g_assert_false(check_nvic_pending(EXTI0_IRQ));
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/* Mask interrupt line EXTI0 */
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exti_writel(EXTI_IMR1, 0x00000000);
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/* Set the corresponding SWIER bit from '0' to '1' */
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exti_writel(EXTI_SWIER1, 0x00000000);
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exti_writel(EXTI_SWIER1, 0x00000001);
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/* Check that the write in SWIER was effective */
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g_assert_cmpuint(exti_readl(EXTI_SWIER1), ==, 0x00000001);
|
||||
/* Check that the pending bit in PR wasn't set */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
||||
/* Check that the interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
||||
|
||||
/* Enable interrupt line EXTI0 */
|
||||
exti_writel(EXTI_IMR1, 0x00000001);
|
||||
|
||||
/* Check that the pending bit in PR wasn't set */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
||||
/* Check that the interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI0_IRQ));
|
||||
|
||||
/*
|
||||
* Testing interrupt line EXTI35
|
||||
* Bit 3 in EXTI_*2 registers (EXTI35) corresponds to PVM 1 Wakeup
|
||||
*/
|
||||
|
||||
enable_nvic_irq(EXTI35_IRQ);
|
||||
/* Check that there are no interrupts already pending in PR */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
|
||||
/* Check that this specific interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
||||
|
||||
/* Mask interrupt line EXTI35 */
|
||||
exti_writel(EXTI_IMR2, 0x00000000);
|
||||
/* Set the corresponding SWIER bit from '0' to '1' */
|
||||
exti_writel(EXTI_SWIER2, 0x00000000);
|
||||
exti_writel(EXTI_SWIER2, 0x00000008);
|
||||
|
||||
/* Check that the write in SWIER was effective */
|
||||
g_assert_cmpuint(exti_readl(EXTI_SWIER2), ==, 0x00000008);
|
||||
/* Check that the pending bit in PR wasn't set */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
|
||||
/* Check that the interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
||||
|
||||
/* Enable interrupt line EXTI35 */
|
||||
exti_writel(EXTI_IMR2, 0x00000008);
|
||||
|
||||
/* Check that the pending bit in PR wasn't set */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR2), ==, 0x00000000);
|
||||
/* Check that the interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI35_IRQ));
|
||||
}
|
||||
|
||||
static void test_masked_interrupt(void)
|
||||
{
|
||||
/*
|
||||
* Test that irq doesn't happen when :
|
||||
* - corresponding bit in IMR isn't set
|
||||
* - SWIER is set to 1 before IMR is set to 1
|
||||
*/
|
||||
|
||||
/*
|
||||
* Testing interrupt line EXTI1
|
||||
* with rising edge from GPIOx pin 1
|
||||
*/
|
||||
|
||||
enable_nvic_irq(EXTI1_IRQ);
|
||||
/* Check that there are no interrupts already pending in PR */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
||||
/* Check that this specific interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
||||
|
||||
/* Mask interrupt line EXTI1 */
|
||||
exti_writel(EXTI_IMR1, 0x00000000);
|
||||
|
||||
/* Configure interrupt on rising edge */
|
||||
exti_writel(EXTI_RTSR1, 0x00000002);
|
||||
|
||||
/* Simulate rising edge from GPIO line 1 */
|
||||
exti_set_irq(1, 1);
|
||||
|
||||
/* Check that the pending bit in PR wasn't set */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
||||
/* Check that the interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
||||
|
||||
/* Enable interrupt line EXTI1 */
|
||||
exti_writel(EXTI_IMR1, 0x00000002);
|
||||
|
||||
/* Check that the pending bit in PR wasn't set */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
||||
/* Check that the interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
||||
}
|
||||
|
||||
static void test_interrupt(void)
|
||||
{
|
||||
/*
|
||||
* Test that we can launch an irq by :
|
||||
* - enabling its line in IMR
|
||||
* - configuring interrupt on rising edge
|
||||
* - and then setting the input line from '0' to '1'
|
||||
*
|
||||
* And that the interruption stays pending in NVIC
|
||||
* even after clearing the pending bit in PR.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Testing interrupt line EXTI1
|
||||
* with rising edge from GPIOx pin 1
|
||||
*/
|
||||
|
||||
enable_nvic_irq(EXTI1_IRQ);
|
||||
/* Check that there are no interrupts already pending in PR */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
||||
/* Check that this specific interrupt isn't pending in NVIC */
|
||||
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
||||
|
||||
/* Enable interrupt line EXTI1 */
|
||||
exti_writel(EXTI_IMR1, 0x00000002);
|
||||
|
||||
/* Configure interrupt on rising edge */
|
||||
exti_writel(EXTI_RTSR1, 0x00000002);
|
||||
|
||||
/* Simulate rising edge from GPIO line 1 */
|
||||
exti_set_irq(1, 1);
|
||||
|
||||
/* Check that the pending bit in PR was set */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000002);
|
||||
/* Check that the interrupt is pending in NVIC */
|
||||
g_assert_true(check_nvic_pending(EXTI1_IRQ));
|
||||
|
||||
/* Clear the pending bit in PR */
|
||||
exti_writel(EXTI_PR1, 0x00000002);
|
||||
|
||||
/* Check that the write in PR was effective */
|
||||
g_assert_cmpuint(exti_readl(EXTI_PR1), ==, 0x00000000);
|
||||
/* Check that the interrupt is still pending in the NVIC */
|
||||
g_assert_true(check_nvic_pending(EXTI1_IRQ));
|
||||
|
||||
/* Clean NVIC */
|
||||
unpend_nvic_irq(EXTI1_IRQ);
|
||||
g_assert_false(check_nvic_pending(EXTI1_IRQ));
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
g_test_init(&argc, &argv, NULL);
|
||||
g_test_set_nonfatal_assertions();
|
||||
qtest_add_func("stm32l4x5/exti/direct_lines", test_direct_lines_write);
|
||||
qtest_add_func("stm32l4x5/exti/reserved_bits", test_reserved_bits_write);
|
||||
qtest_add_func("stm32l4x5/exti/reg_write_read", test_reg_write_read);
|
||||
qtest_add_func("stm32l4x5/exti/no_software_interrupt",
|
||||
test_no_software_interrupt);
|
||||
qtest_add_func("stm32l4x5/exti/software_interrupt",
|
||||
test_software_interrupt);
|
||||
qtest_add_func("stm32l4x5/exti/masked_interrupt", test_masked_interrupt);
|
||||
qtest_add_func("stm32l4x5/exti/interrupt", test_interrupt);
|
||||
qtest_add_func("stm32l4x5/exti/test_edge_selector", test_edge_selector);
|
||||
|
||||
qtest_start("-machine b-l475e-iot01a");
|
||||
ret = g_test_run();
|
||||
qtest_end();
|
||||
|
||||
return ret;
|
||||
}
|
||||
Loading…
Reference in New Issue