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target/mips: Add emulation of DSP ASE for nanoMIPS - part 5 

Add emulation of DSP ASE instructions for nanoMIPS - part 5.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Stefan Markovic 2018-08-02 16:16:29 +02:00 committed by Aleksandar Markovic
parent 8b3698b294
commit 4c75c985d9
1 changed files with 142 additions and 0 deletions
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142
target/mips/translate.c
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@ -17774,6 +17774,144 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
tcg_temp_free(v1_t);
}
static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
int rt, int rs)
{
int ret = rt;
TCGv t0 = tcg_temp_new();
TCGv v0_t = tcg_temp_new();
gen_load_gpr(v0_t, rs);
switch (opc) {
case NM_ABSQ_S_QB:
check_dspr2(ctx);
gen_helper_absq_s_qb(v0_t, v0_t, cpu_env);
gen_store_gpr(v0_t, ret);
break;
case NM_ABSQ_S_PH:
check_dsp(ctx);
gen_helper_absq_s_ph(v0_t, v0_t, cpu_env);
gen_store_gpr(v0_t, ret);
break;
case NM_ABSQ_S_W:
check_dsp(ctx);
gen_helper_absq_s_w(v0_t, v0_t, cpu_env);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQ_W_PHL:
check_dsp(ctx);
tcg_gen_andi_tl(v0_t, v0_t, 0xFFFF0000);
tcg_gen_ext32s_tl(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQ_W_PHR:
check_dsp(ctx);
tcg_gen_andi_tl(v0_t, v0_t, 0x0000FFFF);
tcg_gen_shli_tl(v0_t, v0_t, 16);
tcg_gen_ext32s_tl(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQU_PH_QBL:
check_dsp(ctx);
gen_helper_precequ_ph_qbl(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQU_PH_QBR:
check_dsp(ctx);
gen_helper_precequ_ph_qbr(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQU_PH_QBLA:
check_dsp(ctx);
gen_helper_precequ_ph_qbla(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEQU_PH_QBRA:
check_dsp(ctx);
gen_helper_precequ_ph_qbra(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEU_PH_QBL:
check_dsp(ctx);
gen_helper_preceu_ph_qbl(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEU_PH_QBR:
check_dsp(ctx);
gen_helper_preceu_ph_qbr(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEU_PH_QBLA:
check_dsp(ctx);
gen_helper_preceu_ph_qbla(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_PRECEU_PH_QBRA:
check_dsp(ctx);
gen_helper_preceu_ph_qbra(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_REPLV_PH:
check_dsp(ctx);
tcg_gen_ext16u_tl(v0_t, v0_t);
tcg_gen_shli_tl(t0, v0_t, 16);
tcg_gen_or_tl(v0_t, v0_t, t0);
tcg_gen_ext32s_tl(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_REPLV_QB:
check_dsp(ctx);
tcg_gen_ext8u_tl(v0_t, v0_t);
tcg_gen_shli_tl(t0, v0_t, 8);
tcg_gen_or_tl(v0_t, v0_t, t0);
tcg_gen_shli_tl(t0, v0_t, 16);
tcg_gen_or_tl(v0_t, v0_t, t0);
tcg_gen_ext32s_tl(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_BITREV:
check_dsp(ctx);
gen_helper_bitrev(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_INSV:
check_dsp(ctx);
{
TCGv tv0 = tcg_temp_new();
gen_load_gpr(tv0, rt);
gen_helper_insv(v0_t, cpu_env, v0_t, tv0);
gen_store_gpr(v0_t, ret);
tcg_temp_free(tv0);
}
break;
case NM_RADDU_W_QB:
check_dsp(ctx);
gen_helper_raddu_w_qb(v0_t, v0_t);
gen_store_gpr(v0_t, ret);
break;
case NM_BITSWAP:
gen_bitswap(ctx, OPC_BITSWAP, ret, rs);
break;
case NM_CLO:
gen_cl(ctx, OPC_CLO, ret, rs);
break;
case NM_CLZ:
gen_cl(ctx, OPC_CLZ, ret, rs);
break;
case NM_WSBH:
gen_bshfl(ctx, OPC_WSBH, ret, rs);
break;
default:
generate_exception_end(ctx, EXCP_RI);
break;
}
tcg_temp_free(v0_t);
tcg_temp_free(t0);
}
static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
@ -17795,6 +17933,10 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_POOL32AXF_4:
{
int32_t op1 = extract32(ctx->opcode, 9, 7);
gen_pool32axf_4_nanomips_insn(ctx, op1, rt, rs);
}
break;
case NM_POOL32AXF_5:
switch (extract32(ctx->opcode, 9, 7)) {