mirror of https://github.com/xemu-project/xemu.git
target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alexey Baturo
Alistair Francis
parent
138b5c5f8f
commit
4bbe8033fc
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@ -367,6 +367,8 @@ static void riscv_cpu_reset(DeviceState *dev)
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env->mcause = 0;
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env->pc = env->resetvec;
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env->two_stage_lookup = false;
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/* mmte is supposed to have pm.current hardwired to 1 */
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env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
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#endif
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cs->exception_index = RISCV_EXCP_NONE;
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env->load_res = -1;
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@ -238,6 +238,17 @@ struct CPURISCVState {
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/* True if in debugger mode. */
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bool debugger;
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/*
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* CSRs for PointerMasking extension
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*/
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target_ulong mmte;
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target_ulong mpmmask;
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target_ulong mpmbase;
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target_ulong spmmask;
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target_ulong spmbase;
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target_ulong upmmask;
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target_ulong upmbase;
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#endif
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float_status fp_status;
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@ -192,6 +192,16 @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
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}
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/* Checks if PointerMasking registers could be accessed */
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static RISCVException pointer_masking(CPURISCVState *env, int csrno)
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{
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/* Check if j-ext is present */
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if (riscv_has_ext(env, RVJ)) {
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return RISCV_EXCP_NONE;
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}
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return RISCV_EXCP_ILLEGAL_INST;
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}
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static RISCVException pmp(CPURISCVState *env, int csrno)
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{
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if (riscv_feature(env, RISCV_FEATURE_PMP)) {
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@ -1425,6 +1435,268 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
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return RISCV_EXCP_NONE;
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}
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/*
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* Functions to access Pointer Masking feature registers
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* We have to check if current priv lvl could modify
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* csr in given mode
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*/
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static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
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{
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int csr_priv = get_field(csrno, 0x300);
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int pm_current;
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/*
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* If priv lvls differ that means we're accessing csr from higher priv lvl,
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* so allow the access
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*/
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if (env->priv != csr_priv) {
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return false;
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}
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switch (env->priv) {
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case PRV_M:
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pm_current = get_field(env->mmte, M_PM_CURRENT);
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break;
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case PRV_S:
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pm_current = get_field(env->mmte, S_PM_CURRENT);
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break;
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case PRV_U:
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pm_current = get_field(env->mmte, U_PM_CURRENT);
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break;
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default:
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g_assert_not_reached();
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}
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/* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
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return !pm_current;
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}
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static RISCVException read_mmte(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->mmte & MMTE_MASK;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_mmte(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mstatus;
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target_ulong wpri_val = val & MMTE_MASK;
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if (val != wpri_val) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
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"MMTE: WPRI violation written 0x", val,
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"vs expected 0x", wpri_val);
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}
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/* for machine mode pm.current is hardwired to 1 */
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wpri_val |= MMTE_M_PM_CURRENT;
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/* hardwiring pm.instruction bit to 0, since it's not supported yet */
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wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
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env->mmte = wpri_val | PM_EXT_DIRTY;
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/* Set XS and SD bits, since PM CSRs are dirty */
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mstatus = env->mstatus | MSTATUS_XS;
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write_mstatus(env, csrno, mstatus);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_smte(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->mmte & SMTE_MASK;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_smte(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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target_ulong wpri_val = val & SMTE_MASK;
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if (val != wpri_val) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
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"SMTE: WPRI violation written 0x", val,
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"vs expected 0x", wpri_val);
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}
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/* if pm.current==0 we can't modify current PM CSRs */
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if (check_pm_current_disabled(env, csrno)) {
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return RISCV_EXCP_NONE;
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}
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wpri_val |= (env->mmte & ~SMTE_MASK);
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write_mmte(env, csrno, wpri_val);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_umte(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->mmte & UMTE_MASK;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_umte(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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target_ulong wpri_val = val & UMTE_MASK;
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if (val != wpri_val) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
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"UMTE: WPRI violation written 0x", val,
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"vs expected 0x", wpri_val);
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}
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if (check_pm_current_disabled(env, csrno)) {
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return RISCV_EXCP_NONE;
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}
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wpri_val |= (env->mmte & ~UMTE_MASK);
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write_mmte(env, csrno, wpri_val);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->mpmmask;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mstatus;
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env->mpmmask = val;
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env->mmte |= PM_EXT_DIRTY;
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/* Set XS and SD bits, since PM CSRs are dirty */
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mstatus = env->mstatus | MSTATUS_XS;
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write_mstatus(env, csrno, mstatus);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_spmmask(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->spmmask;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_spmmask(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mstatus;
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/* if pm.current==0 we can't modify current PM CSRs */
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if (check_pm_current_disabled(env, csrno)) {
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return RISCV_EXCP_NONE;
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}
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env->spmmask = val;
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env->mmte |= PM_EXT_DIRTY;
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/* Set XS and SD bits, since PM CSRs are dirty */
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mstatus = env->mstatus | MSTATUS_XS;
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write_mstatus(env, csrno, mstatus);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_upmmask(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->upmmask;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_upmmask(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mstatus;
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/* if pm.current==0 we can't modify current PM CSRs */
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if (check_pm_current_disabled(env, csrno)) {
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return RISCV_EXCP_NONE;
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}
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env->upmmask = val;
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env->mmte |= PM_EXT_DIRTY;
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/* Set XS and SD bits, since PM CSRs are dirty */
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mstatus = env->mstatus | MSTATUS_XS;
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write_mstatus(env, csrno, mstatus);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->mpmbase;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mstatus;
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env->mpmbase = val;
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env->mmte |= PM_EXT_DIRTY;
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/* Set XS and SD bits, since PM CSRs are dirty */
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mstatus = env->mstatus | MSTATUS_XS;
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write_mstatus(env, csrno, mstatus);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_spmbase(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->spmbase;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_spmbase(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mstatus;
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/* if pm.current==0 we can't modify current PM CSRs */
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if (check_pm_current_disabled(env, csrno)) {
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return RISCV_EXCP_NONE;
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}
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env->spmbase = val;
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env->mmte |= PM_EXT_DIRTY;
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/* Set XS and SD bits, since PM CSRs are dirty */
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mstatus = env->mstatus | MSTATUS_XS;
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write_mstatus(env, csrno, mstatus);
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_upmbase(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->upmbase;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_upmbase(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mstatus;
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/* if pm.current==0 we can't modify current PM CSRs */
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if (check_pm_current_disabled(env, csrno)) {
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return RISCV_EXCP_NONE;
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}
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env->upmbase = val;
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env->mmte |= PM_EXT_DIRTY;
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/* Set XS and SD bits, since PM CSRs are dirty */
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mstatus = env->mstatus | MSTATUS_XS;
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write_mstatus(env, csrno, mstatus);
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return RISCV_EXCP_NONE;
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}
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#endif
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/*
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@ -1659,6 +1931,19 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
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[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
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/* User Pointer Masking */
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[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
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[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
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[CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
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/* Machine Pointer Masking */
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[CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
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[CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
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[CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
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/* Supervisor Pointer Masking */
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[CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
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[CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
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[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
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/* Performance Counters */
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[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
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[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
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