From 10f9f1fbed11e520e6fd71f02cd71f0e9c759b69 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 8 Nov 2019 15:11:34 +0100 Subject: [PATCH 1/2] hw/block/pflash: Remove dynamic field width from trace events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. We previously passed to the trace API 'width << 1' as the number of hex characters to display (the dynamic field width). We don't need this anymore. Instead, display the size of bytes accessed. Fixes: e8aa2d95ea ("pflash: Simplify trace_pflash_io_read/write") Fixes: c1474acd5d ("pflash: Simplify trace_pflash_data_read/write") Reported-by: Eric Blake Reviewed-by: Eric Blake Reviewed-by: Richard Henderson Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 8 ++++---- hw/block/pflash_cfi02.c | 8 ++++---- hw/block/trace-events | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 566c0acb77..54e6ebd385 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -276,7 +276,7 @@ static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset, DPRINTF("BUG in %s\n", __func__); abort(); } - trace_pflash_data_read(offset, width << 1, ret); + trace_pflash_data_read(offset, width, ret); return ret; } @@ -389,7 +389,7 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset, break; } - trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle); + trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle); return ret; } @@ -414,7 +414,7 @@ static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset, { uint8_t *p = pfl->storage; - trace_pflash_data_write(offset, width << 1, value, pfl->counter); + trace_pflash_data_write(offset, width, value, pfl->counter); switch (width) { case 1: p[offset] = value; @@ -453,7 +453,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, cmd = value; - trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); + trace_pflash_io_write(offset, width, value, pfl->wcycle); if (!pfl->wcycle) { /* Set the device in I/O access mode */ memory_region_rom_device_set_romd(&pfl->mem, false); diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 4baca701b7..c7d92c3e79 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -260,7 +260,7 @@ static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset, { uint8_t *p = (uint8_t *)pfl->storage + offset; uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); - trace_pflash_data_read(offset, width << 1, ret); + trace_pflash_data_read(offset, width, ret); return ret; } @@ -385,7 +385,7 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) } break; } - trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle); + trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle); return ret; } @@ -432,7 +432,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value, uint8_t *p; uint8_t cmd; - trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); + trace_pflash_io_write(offset, width, value, pfl->wcycle); cmd = value; if (pfl->cmd != 0xA0) { /* Reset does nothing during chip erase and sector erase. */ @@ -542,7 +542,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value, } goto reset_flash; } - trace_pflash_data_write(offset, width << 1, value, 0); + trace_pflash_data_write(offset, width, value, 0); if (!pfl->ro) { p = (uint8_t *)pfl->storage + offset; if (pfl->be) { diff --git a/hw/block/trace-events b/hw/block/trace-events index 13d1b21dd4..c03e80c2c9 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -8,10 +8,10 @@ fdc_ioport_write(uint8_t reg, uint8_t value) "write reg 0x%02x val 0x%02x" # pflash_cfi01.c pflash_reset(void) "reset" pflash_timer_expired(uint8_t cmd) "command 0x%02x done" -pflash_io_read(uint64_t offset, int width, int fmt_width, uint32_t value, uint8_t cmd, uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x cmd:0x%02x wcycle:%u" -pflash_io_write(uint64_t offset, int width, int fmt_width, uint32_t value, uint8_t wcycle) "offset:0x%04"PRIx64" width:%d value:0x%0*x wcycle:%u" -pflash_data_read(uint64_t offset, int width, uint32_t value) "data offset:0x%04"PRIx64" value:0x%0*x" -pflash_data_write(uint64_t offset, int width, uint32_t value, uint64_t counter) "data offset:0x%04"PRIx64" value:0x%0*x counter:0x%016"PRIx64 +pflash_io_read(uint64_t offset, unsigned size, uint32_t value, uint8_t cmd, uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x cmd:0x%02x wcycle:%u" +pflash_io_write(uint64_t offset, unsigned size, uint32_t value, uint8_t wcycle) "offset:0x%04"PRIx64" size:%u value:0x%04x wcycle:%u" +pflash_data_read(uint64_t offset, unsigned size, uint32_t value) "data offset:0x%04"PRIx64" size:%u value:0x%04x" +pflash_data_write(uint64_t offset, unsigned size, uint32_t value, uint64_t counter) "data offset:0x%04"PRIx64" size:%u value:0x%04x counter:0x%016"PRIx64 pflash_manufacturer_id(uint16_t id) "Read Manufacturer ID: 0x%04x" pflash_device_id(uint16_t id) "Read Device ID: 0x%04x" pflash_device_info(uint64_t offset) "Read Device Information offset:0x%04"PRIx64 From abc7cf36559f953777faf27d2e0dfb561ac533a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 8 Nov 2019 15:13:59 +0100 Subject: [PATCH 2/2] hw/mips/gt64xxx: Remove dynamic field width from trace events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. We previously passed to the trace API 'width << 1' as the number of hex characters to display (the dynamic field width). We don't need this anymore. Instead, display the size of bytes accessed. Fixes: ab6bff424f ("gt64xxx_pci: Convert debug printf to trace events") Reported-by: Eric Blake Reviewed-by: Eric Blake Reviewed-by: Richard Henderson Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 16 ++++++++-------- hw/mips/trace-events | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 5cab9c1ee1..f1af840d8e 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr, /* not really implemented */ s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); - trace_gt64120_write("INTRCAUSE", size << 1, val); + trace_gt64120_write("INTRCAUSE", size, val); break; case GT_INTRMASK: s->regs[saddr] = val & 0x3c3ffffe; - trace_gt64120_write("INTRMASK", size << 1, val); + trace_gt64120_write("INTRMASK", size, val); break; case GT_PCI0_ICMASK: s->regs[saddr] = val & 0x03fffffe; - trace_gt64120_write("ICMASK", size << 1, val); + trace_gt64120_write("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: s->regs[saddr] = val & 0x0000003f; - trace_gt64120_write("SERR0MASK", size << 1, val); + trace_gt64120_write("SERR0MASK", size, val); break; /* Reserved when only PCI_0 is configured. */ @@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque, /* Interrupts */ case GT_INTRCAUSE: val = s->regs[saddr]; - trace_gt64120_read("INTRCAUSE", size << 1, val); + trace_gt64120_read("INTRCAUSE", size, val); break; case GT_INTRMASK: val = s->regs[saddr]; - trace_gt64120_read("INTRMASK", size << 1, val); + trace_gt64120_read("INTRMASK", size, val); break; case GT_PCI0_ICMASK: val = s->regs[saddr]; - trace_gt64120_read("ICMASK", size << 1, val); + trace_gt64120_read("ICMASK", size, val); break; case GT_PCI0_SERR0MASK: val = s->regs[saddr]; - trace_gt64120_read("SERR0MASK", size << 1, val); + trace_gt64120_read("SERR0MASK", size, val); break; /* Reserved when only PCI_0 is configured. */ diff --git a/hw/mips/trace-events b/hw/mips/trace-events index 75d4c73f2e..321933283f 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,4 @@ # gt64xxx.c -gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64 -gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64 +gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 +gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64