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target-mips: add mips32r6-generic CPU definition
Define a new CPU definition supporting MIPS32 Release 6 ISA and microMIPS32 Release 6 ISA. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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@ -424,6 +424,43 @@ static const mips_def_t mips_defs[] =
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.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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/* A generic CPU supporting MIPS32 Release 6 ISA.
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FIXME: Support IEEE 754-2008 FP.
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Eventually this should be replaced by a real CPU model. */
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.name = "mips32r6-generic",
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.CP0_PRid = 0x00010000,
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
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(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
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(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
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(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
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(2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
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(1 << CP0C3_RXI) | (1U << CP0C3_M),
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.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
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(3 << CP0C4_IE) | (1U << CP0C4_M),
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.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),
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.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
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(1 << CP0C5_UFE),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 0,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x3058FF1F,
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.CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
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(1U << CP0PG_RIE),
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.CP0_PageGrain_rw_bitmask = 0,
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.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
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(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
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(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
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.mmu_type = MMU_TYPE_R4000,
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},
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#if defined(TARGET_MIPS64)
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{
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.name = "R4000",
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