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* Avoid qemu_get_cpu() and first_cpu, and use properties instead 

* Mirror next-cube bios to address 0
 * Instantiate ESP SCSI controller in the next-cube machine
 * Fix URL in the next-cube avocado test
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Merge tag 'm68k-pull-2023-11-02' of https://gitlab.com/huth/qemu into staging

* Avoid qemu_get_cpu() and first_cpu, and use properties instead
* Mirror next-cube bios to address 0
* Instantiate ESP SCSI controller in the next-cube machine
* Fix URL in the next-cube avocado test

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# gpg: Signature made Thu 02 Nov 2023 17:37:05 HKT
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "huth@tuxfamily.org"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'm68k-pull-2023-11-02' of https://gitlab.com/huth/qemu:
  tests/avocado/machine_m68k_nextcube: Fix the download URL for the ROM image
  m68k: Instantiate the ESP SCSI controller for the NeXTcube machine
  hw/m68k/next-cube: Mirror BIOS to address 0
  hw/char/mcf_uart: Have mcf_uart_create() return DeviceState
  hw/m68k/virt: Do not open-code sysbus_create_simple()
  hw/m68k/next-cube: Do not open-code sysbus_create_simple()
  hw/m68k/mcf_intc: Pass CPU using QOM link property
  hw/m68k/mcf_intc: Expose MMIO region via SysBus API
  hw/m68k/mcf5206: Pass CPU using QOM link property
  hw/m68k/irqc: Pass CPU using QOM link property

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-02 18:21:21 +08:00
parent 6c9ae1ce82 a35c20961b
commit 4a6a6cb60d
11 changed files with 172 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
hw/char/mcf_uart.c
View File

@ -342,25 +342,26 @@ static void mcf_uart_register(void)
type_init(mcf_uart_register)
void *mcf_uart_init(qemu_irq irq, Chardev *chrdrv)
DeviceState *mcf_uart_create(qemu_irq irq, Chardev *chrdrv)
{
DeviceState *dev;
DeviceState *dev;
dev = qdev_new(TYPE_MCF_UART);
if (chrdrv) {
qdev_prop_set_chr(dev, "chardev", chrdrv);
}
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
return dev;
}
void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chrdrv)
DeviceState *mcf_uart_create_mmap(hwaddr base, qemu_irq irq, Chardev *chrdrv)
{
DeviceState *dev;
DeviceState *dev;
dev = mcf_uart_init(irq, chrdrv);
dev = mcf_uart_create(irq, chrdrv);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return dev;
}

10
hw/intc/m68k_irqc.c
View File

@ -11,6 +11,7 @@
#include "cpu.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/qdev-properties.h"
#include "hw/nmi.h"
#include "hw/intc/intc.h"
#include "hw/intc/m68k_irqc.h"
@ -35,7 +36,7 @@ static void m68k_irqc_print_info(InterruptStatsProvider *obj, Monitor *mon)
static void m68k_set_irq(void *opaque, int irq, int level)
{
M68KIRQCState *s = opaque;
M68kCPU *cpu = M68K_CPU(first_cpu);
M68kCPU *cpu = M68K_CPU(s->cpu);
int i;
if (level) {
@ -85,12 +86,19 @@ static const VMStateDescription vmstate_m68k_irqc = {
}
};
static Property m68k_irqc_properties[] = {
DEFINE_PROP_LINK("m68k-cpu", M68KIRQCState, cpu,
TYPE_M68K_CPU, ArchCPU *),
DEFINE_PROP_END_OF_LIST(),
};
static void m68k_irqc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(oc);
device_class_set_props(dc, m68k_irqc_properties);
nc->nmi_monitor_handler = m68k_nmi;
dc->reset = m68k_irqc_reset;
dc->vmsd = &vmstate_m68k_irqc;

6
hw/m68k/an5206.c
View File

@ -20,12 +20,14 @@
#define AN5206_MBAR_ADDR 0x10000000
#define AN5206_RAMBAR_ADDR 0x20000000
static void mcf5206_init(MemoryRegion *sysmem, uint32_t base)
static void mcf5206_init(M68kCPU *cpu, MemoryRegion *sysmem, uint32_t base)
{
DeviceState *dev;
SysBusDevice *s;
dev = qdev_new(TYPE_MCF5206_MBAR);
object_property_set_link(OBJECT(dev), "m68k-cpu",
OBJECT(cpu), &error_abort);
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
@ -60,7 +62,7 @@ static void an5206_init(MachineState *machine)
memory_region_init_ram(sram, NULL, "an5206.sram", 512, &error_fatal);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(address_space_mem, AN5206_MBAR_ADDR);
mcf5206_init(cpu, address_space_mem, AN5206_MBAR_ADDR);
/* Load kernel. */
if (!kernel_filename) {

15
hw/m68k/mcf5206.c
View File

@ -10,6 +10,7 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "cpu.h"
#include "hw/qdev-properties.h"
#include "hw/boards.h"
#include "hw/irq.h"
#include "hw/m68k/mcf.h"
@ -167,7 +168,7 @@ typedef struct {
MemoryRegion iomem;
qemu_irq *pic;
m5206_timer_state *timer[2];
void *uart[2];
DeviceState *uart[2];
uint8_t scr;
uint8_t icr[14];
uint16_t imr; /* 1 == interrupt is masked. */
@ -599,15 +600,21 @@ static void mcf5206_mbar_realize(DeviceState *dev, Error **errp)
s->pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14);
s->timer[0] = m5206_timer_init(s->pic[9]);
s->timer[1] = m5206_timer_init(s->pic[10]);
s->uart[0] = mcf_uart_init(s->pic[12], serial_hd(0));
s->uart[1] = mcf_uart_init(s->pic[13], serial_hd(1));
s->cpu = M68K_CPU(qemu_get_cpu(0));
s->uart[0] = mcf_uart_create(s->pic[12], serial_hd(0));
s->uart[1] = mcf_uart_create(s->pic[13], serial_hd(1));
}
static Property mcf5206_mbar_properties[] = {
DEFINE_PROP_LINK("m68k-cpu", m5206_mbar_state, cpu,
TYPE_M68K_CPU, M68kCPU *),
DEFINE_PROP_END_OF_LIST(),
};
static void mcf5206_mbar_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_props(dc, mcf5206_mbar_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->desc = "MCF5206 system integration module";
dc->realize = mcf5206_mbar_realize;

6
hw/m68k/mcf5208.c
View File

@ -261,9 +261,9 @@ static void mcf5208evb_init(MachineState *machine)
/* Internal peripherals. */
pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0));
mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1));
mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2));
mcf_uart_create_mmap(0xfc060000, pic[26], serial_hd(0));
mcf_uart_create_mmap(0xfc064000, pic[27], serial_hd(1));
mcf_uart_create_mmap(0xfc068000, pic[28], serial_hd(2));
mcf5208_sys_init(address_space_mem, pic);

21
hw/m68k/mcf_intc.c
View File

@ -14,6 +14,7 @@
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "hw/m68k/mcf.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
#define TYPE_MCF_INTC "mcf-intc"
@ -173,12 +174,20 @@ static void mcf_intc_instance_init(Object *obj)
mcf_intc_state *s = MCF_INTC(obj);
memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
}
static Property mcf_intc_properties[] = {
DEFINE_PROP_LINK("m68k-cpu", mcf_intc_state, cpu,
TYPE_M68K_CPU, M68kCPU *),
DEFINE_PROP_END_OF_LIST(),
};
static void mcf_intc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_props(dc, mcf_intc_properties);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->reset = mcf_intc_reset;
}
@ -203,15 +212,13 @@ qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
M68kCPU *cpu)
{
DeviceState *dev;
mcf_intc_state *s;
dev = qdev_new(TYPE_MCF_INTC);
object_property_set_link(OBJECT(dev), "m68k-cpu",
OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
memory_region_add_subregion(sysmem, base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
s = MCF_INTC(dev);
s->cpu = cpu;
memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);
return qemu_allocate_irqs(mcf_intc_set_irq, dev, 64);
}

130
hw/m68k/next-cube.c
View File

@ -90,10 +90,13 @@ struct NeXTPC {
uint32_t scr1;
uint32_t scr2;
uint8_t scsi_csr_1;
uint8_t scsi_csr_2;
uint32_t int_mask;
uint32_t int_status;
uint8_t scsi_csr_1;
uint8_t scsi_csr_2;
qemu_irq scsi_reset;
qemu_irq scsi_dma;
NextRtc rtc;
};
@ -466,7 +469,7 @@ static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value)
DPRINTF("SCSICSR FIFO Flush\n");
/* will have to add another irq to the esp if this is needed */
/* esp_puflush_fifo(esp_g); */
/* qemu_irq_pulse(s->scsi_dma); */
qemu_irq_pulse(s->scsi_dma);
}
if (value & SCSICSR_ENABLE) {
@ -486,9 +489,9 @@ static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value)
if (value & SCSICSR_RESET) {
DPRINTF("SCSICSR Reset\n");
/* I think this should set DMADIR. CPUDMA and INTMASK to 0 */
/* qemu_irq_raise(s->scsi_reset); */
/* s->scsi_csr_1 &= ~(SCSICSR_INTMASK |0x80|0x1); */
qemu_irq_raise(s->scsi_reset);
s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1);
qemu_irq_lower(s->scsi_reset);
}
if (value & SCSICSR_DMADIR) {
DPRINTF("SCSICSR DMAdir\n");
@ -496,10 +499,11 @@ static void scr_writeb(NeXTPC *s, hwaddr addr, uint32_t value)
if (value & SCSICSR_CPUDMA) {
DPRINTF("SCSICSR CPUDMA\n");
/* qemu_irq_raise(s->scsi_dma); */
s->int_status |= 0x4000000;
} else {
/* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */
s->int_status &= ~(0x4000000);
/* qemu_irq_lower(s->scsi_dma); */
}
if (value & SCSICSR_INTMASK) {
DPRINTF("SCSICSR INTMASK\n");
@ -828,6 +832,103 @@ static void next_irq(void *opaque, int number, int level)
}
}
static void nextdma_write(void *opaque, uint8_t *buf, int size, int type)
{
uint32_t base_addr;
int irq = 0;
uint8_t align = 16;
NeXTState *next_state = NEXT_MACHINE(qdev_get_machine());
if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) {
align = 32;
}
/* Most DMA is supposedly 16 byte aligned */
if ((size % align) != 0) {
size -= size % align;
size += align;
}
/*
* prom sets the dma start using initbuf while the bootloader uses next
* so we check to see if initbuf is 0
*/
if (next_state->dma[type].next_initbuf == 0) {
base_addr = next_state->dma[type].next;
} else {
base_addr = next_state->dma[type].next_initbuf;
}
cpu_physical_memory_write(base_addr, buf, size);
next_state->dma[type].next_initbuf = 0;
/* saved limit is checked to calculate packet size by both, rom and netbsd */
next_state->dma[type].saved_limit = (next_state->dma[type].next + size);
next_state->dma[type].saved_next = (next_state->dma[type].next);
/*
* 32 bytes under savedbase seems to be some kind of register
* of which the purpose is unknown as of yet
*/
/* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */
if (!(next_state->dma[type].csr & DMA_SUPDATE)) {
next_state->dma[type].next = next_state->dma[type].start;
next_state->dma[type].limit = next_state->dma[type].stop;
}
/* Set dma registers and raise an irq */
next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */
switch (type) {
case NEXTDMA_SCSI:
irq = NEXT_SCSI_DMA_I;
break;
}
next_irq(opaque, irq, 1);
next_irq(opaque, irq, 0);
}
static void nextscsi_read(void *opaque, uint8_t *buf, int len)
{
DPRINTF("SCSI READ: %x\n", len);
abort();
}
static void nextscsi_write(void *opaque, uint8_t *buf, int size)
{
DPRINTF("SCSI WRITE: %i\n", size);
nextdma_write(opaque, buf, size, NEXTDMA_SCSI);
}
static void next_scsi_init(DeviceState *pcdev, M68kCPU *cpu)
{
struct NeXTPC *next_pc = NEXT_PC(pcdev);
DeviceState *dev;
SysBusDevice *sysbusdev;
SysBusESPState *sysbus_esp;
ESPState *esp;
dev = qdev_new(TYPE_SYSBUS_ESP);
sysbus_esp = SYSBUS_ESP(dev);
esp = &sysbus_esp->esp;
esp->dma_memory_read = nextscsi_read;
esp->dma_memory_write = nextscsi_write;
esp->dma_opaque = pcdev;
sysbus_esp->it_shift = 0;
esp->dma_enabled = 1;
sysbusdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbusdev, &error_fatal);
sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(pcdev, NEXT_SCSI_I));
sysbus_mmio_map(sysbusdev, 0, 0x2114000);
next_pc->scsi_reset = qdev_get_gpio_in(dev, 0);
next_pc->scsi_dma = qdev_get_gpio_in(dev, 1);
scsi_bus_legacy_handle_cmdline(&esp->bus);
}
static void next_escc_init(DeviceState *pcdev)
{
DeviceState *dev;
@ -945,12 +1046,12 @@ static void next_cube_init(MachineState *machine)
M68kCPU *cpu;
CPUM68KState *env;
MemoryRegion *rom = g_new(MemoryRegion, 1);
MemoryRegion *rom2 = g_new(MemoryRegion, 1);
MemoryRegion *dmamem = g_new(MemoryRegion, 1);
MemoryRegion *bmapm1 = g_new(MemoryRegion, 1);
MemoryRegion *bmapm2 = g_new(MemoryRegion, 1);
MemoryRegion *sysmem = get_system_memory();
const char *bios_name = machine->firmware ?: ROM_FILE;
DeviceState *dev;
DeviceState *pcdev;
/* Initialize the cpu core */
@ -974,9 +1075,7 @@ static void next_cube_init(MachineState *machine)
memory_region_add_subregion(sysmem, 0x04000000, machine->ram);
/* Framebuffer */
dev = qdev_new(TYPE_NEXTFB);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0B000000);
sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL);
/* MMIO */
sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000);
@ -993,14 +1092,13 @@ static void next_cube_init(MachineState *machine)
memory_region_add_subregion(sysmem, 0x820c0000, bmapm2);
/* KBD */
dev = qdev_new(TYPE_NEXTKBD);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x0200e000);
sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL);
/* Load ROM here */
/* still not sure if the rom should also be mapped at 0x0*/
memory_region_init_rom(rom, NULL, "next.rom", 0x20000, &error_fatal);
memory_region_add_subregion(sysmem, 0x01000000, rom);
memory_region_init_alias(rom2, NULL, "next.rom2", rom, 0x0, 0x20000);
memory_region_add_subregion(sysmem, 0x0, rom2);
if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) {
if (!qtest_enabled()) {
error_report("Failed to load firmware '%s'.", bios_name);
@ -1024,6 +1122,7 @@ static void next_cube_init(MachineState *machine)
/* TODO: */
/* Network */
/* SCSI */
next_scsi_init(pcdev, cpu);
/* DMA */
memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5000);
@ -1036,6 +1135,7 @@ static void next_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "NeXT Cube";
mc->init = next_cube_init;
mc->block_default_type = IF_SCSI;
mc->default_ram_size = RAM_SIZE;
mc->default_ram_id = "next.ram";
mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");

9
hw/m68k/virt.c
View File

@ -155,6 +155,8 @@ static void virt_init(MachineState *machine)
/* IRQ Controller */
irqc_dev = qdev_new(TYPE_M68K_IRQC);
object_property_set_link(OBJECT(irqc_dev), "m68k-cpu",
OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(irqc_dev), &error_fatal);
/*
@ -199,11 +201,8 @@ static void virt_init(MachineState *machine)
sysbus_connect_irq(sysbus, 0, PIC_GPIO(VIRT_GF_TTY_IRQ_BASE));
/* virt controller */
dev = qdev_new(TYPE_VIRT_CTRL);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(sysbus, &error_fatal);
sysbus_mmio_map(sysbus, 0, VIRT_CTRL_MMIO_BASE);
sysbus_connect_irq(sysbus, 0, PIC_GPIO(VIRT_CTRL_IRQ_BASE));
dev = sysbus_create_simple(TYPE_VIRT_CTRL, VIRT_CTRL_MMIO_BASE,
PIC_GPIO(VIRT_CTRL_IRQ_BASE));
/* virtio-mmio */
io_base = VIRT_VIRTIO_MMIO_BASE;

1
include/hw/intc/m68k_irqc.h
View File

@ -33,6 +33,7 @@ typedef struct M68KIRQCState {
SysBusDevice parent_obj;
uint8_t ipr;
ArchCPU *cpu;
/* statistics */
uint64_t stats_irq_count[M68K_IRQC_LEVEL_NUM];

4
include/hw/m68k/mcf.h
View File

@ -10,8 +10,8 @@ uint64_t mcf_uart_read(void *opaque, hwaddr addr,
unsigned size);
void mcf_uart_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, Chardev *chr);
void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chr);
DeviceState *mcf_uart_create(qemu_irq irq, Chardev *chr);
DeviceState *mcf_uart_create_mmap(hwaddr base, qemu_irq irq, Chardev *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,

4
tests/avocado/machine_m68k_nextcube.py
View File

@ -30,8 +30,8 @@ class NextCubeMachine(QemuSystemTest):
timeout = 15
def check_bootrom_framebuffer(self, screenshot_path):
rom_url = ('http://www.nextcomputers.org/NeXTfiles/Software/ROM_Files/'
'68040_Non-Turbo_Chipset/Rev_2.5_v66.BIN')
rom_url = ('https://sourceforge.net/p/previous/code/1350/tree/'
'trunk/src/Rev_2.5_v66.BIN?format=raw')
rom_hash = 'b3534796abae238a0111299fc406a9349f7fee24'
rom_path = self.fetch_asset(rom_url, asset_hash=rom_hash)