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hw/arm/sbsa-ref: Simplify by moving the gic in the machine state 

Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20191206162303.30338-1-philmd@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2019-12-06 17:23:03 +01:00 committed by Peter Maydell
parent 0d57b49992
commit 48ba18e6d3
1 changed files with 42 additions and 44 deletions
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86
hw/arm/sbsa-ref.c
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@ -89,6 +89,7 @@ typedef struct {
void *fdt; void *fdt;
int fdt_size; int fdt_size;
int psci_conduit; int psci_conduit;
DeviceState *gic;
PFlashCFI01 *flash[2]; PFlashCFI01 *flash[2];
} SBSAMachineState; } SBSAMachineState;
@ -328,10 +329,9 @@ static void create_secure_ram(SBSAMachineState *sms,
memory_region_add_subregion(secure_sysmem, base, secram); memory_region_add_subregion(secure_sysmem, base, secram);
} }
static void create_gic(SBSAMachineState *sms, qemu_irq *pic) static void create_gic(SBSAMachineState *sms)
{ {
unsigned int smp_cpus = MACHINE(sms)->smp.cpus; unsigned int smp_cpus = MACHINE(sms)->smp.cpus;
DeviceState *gicdev;
SysBusDevice *gicbusdev; SysBusDevice *gicbusdev;
const char *gictype; const char *gictype;
uint32_t redist0_capacity, redist0_count; uint32_t redist0_capacity, redist0_count;
@ -339,25 +339,25 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
gictype = gicv3_class_name(); gictype = gicv3_class_name();
gicdev = qdev_create(NULL, gictype); sms->gic = qdev_create(NULL, gictype);
qdev_prop_set_uint32(gicdev, "revision", 3); qdev_prop_set_uint32(sms->gic, "revision", 3);
qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus); qdev_prop_set_uint32(sms->gic, "num-cpu", smp_cpus);
/* /*
* Note that the num-irq property counts both internal and external * Note that the num-irq property counts both internal and external
* interrupts; there are always 32 of the former (mandated by GIC spec). * interrupts; there are always 32 of the former (mandated by GIC spec).
*/ */
qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32); qdev_prop_set_uint32(sms->gic, "num-irq", NUM_IRQS + 32);
qdev_prop_set_bit(gicdev, "has-security-extensions", true); qdev_prop_set_bit(sms->gic, "has-security-extensions", true);
redist0_capacity = redist0_capacity =
sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE; sbsa_ref_memmap[SBSA_GIC_REDIST].size / GICV3_REDIST_SIZE;
redist0_count = MIN(smp_cpus, redist0_capacity); redist0_count = MIN(smp_cpus, redist0_capacity);
qdev_prop_set_uint32(gicdev, "len-redist-region-count", 1); qdev_prop_set_uint32(sms->gic, "len-redist-region-count", 1);
qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count); qdev_prop_set_uint32(sms->gic, "redist-region-count[0]", redist0_count);
qdev_init_nofail(gicdev); qdev_init_nofail(sms->gic);
gicbusdev = SYS_BUS_DEVICE(gicdev); gicbusdev = SYS_BUS_DEVICE(sms->gic);
sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base); sysbus_mmio_map(gicbusdev, 0, sbsa_ref_memmap[SBSA_GIC_DIST].base);
sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base); sysbus_mmio_map(gicbusdev, 1, sbsa_ref_memmap[SBSA_GIC_REDIST].base);
@ -383,15 +383,15 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
qdev_connect_gpio_out(cpudev, irq, qdev_connect_gpio_out(cpudev, irq,
qdev_get_gpio_in(gicdev, qdev_get_gpio_in(sms->gic,
ppibase + timer_irq[irq])); ppibase + timer_irq[irq]));
} }
qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
qdev_get_gpio_in(gicdev, ppibase qdev_get_gpio_in(sms->gic, ppibase
+ ARCH_GIC_MAINT_IRQ)); + ARCH_GIC_MAINT_IRQ));
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
qdev_get_gpio_in(gicdev, ppibase qdev_get_gpio_in(sms->gic, ppibase
+ VIRTUAL_PMU_IRQ)); + VIRTUAL_PMU_IRQ));
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
@ -402,13 +402,9 @@ static void create_gic(SBSAMachineState *sms, qemu_irq *pic)
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
} }
for (i = 0; i < NUM_IRQS; i++) {
pic[i] = qdev_get_gpio_in(gicdev, i);
}
} }
static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart, static void create_uart(const SBSAMachineState *sms, int uart,
MemoryRegion *mem, Chardev *chr) MemoryRegion *mem, Chardev *chr)
{ {
hwaddr base = sbsa_ref_memmap[uart].base; hwaddr base = sbsa_ref_memmap[uart].base;
@ -420,15 +416,15 @@ static void create_uart(const SBSAMachineState *sms, qemu_irq *pic, int uart,
qdev_init_nofail(dev); qdev_init_nofail(dev);
memory_region_add_subregion(mem, base, memory_region_add_subregion(mem, base,
sysbus_mmio_get_region(s, 0)); sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, pic[irq]); sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq));
} }
static void create_rtc(const SBSAMachineState *sms, qemu_irq *pic) static void create_rtc(const SBSAMachineState *sms)
{ {
hwaddr base = sbsa_ref_memmap[SBSA_RTC].base; hwaddr base = sbsa_ref_memmap[SBSA_RTC].base;
int irq = sbsa_ref_irqmap[SBSA_RTC]; int irq = sbsa_ref_irqmap[SBSA_RTC];
sysbus_create_simple("pl031", base, pic[irq]); sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq));
} }
static DeviceState *gpio_key_dev; static DeviceState *gpio_key_dev;
@ -442,13 +438,14 @@ static Notifier sbsa_ref_powerdown_notifier = {
.notify = sbsa_ref_powerdown_req .notify = sbsa_ref_powerdown_req
}; };
static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic) static void create_gpio(const SBSAMachineState *sms)
{ {
DeviceState *pl061_dev; DeviceState *pl061_dev;
hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base; hwaddr base = sbsa_ref_memmap[SBSA_GPIO].base;
int irq = sbsa_ref_irqmap[SBSA_GPIO]; int irq = sbsa_ref_irqmap[SBSA_GPIO];
pl061_dev = sysbus_create_simple("pl061", base, pic[irq]); pl061_dev = sysbus_create_simple("pl061", base,
qdev_get_gpio_in(sms->gic, irq));
gpio_key_dev = sysbus_create_simple("gpio-key", -1, gpio_key_dev = sysbus_create_simple("gpio-key", -1,
qdev_get_gpio_in(pl061_dev, 3)); qdev_get_gpio_in(pl061_dev, 3));
@ -457,7 +454,7 @@ static void create_gpio(const SBSAMachineState *sms, qemu_irq *pic)
qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier); qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier);
} }
static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic) static void create_ahci(const SBSAMachineState *sms)
{ {
hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base; hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
int irq = sbsa_ref_irqmap[SBSA_AHCI]; int irq = sbsa_ref_irqmap[SBSA_AHCI];
@ -471,7 +468,7 @@ static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS); qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
qdev_init_nofail(dev); qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irq]); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
sysahci = SYSBUS_AHCI(dev); sysahci = SYSBUS_AHCI(dev);
ahci = &sysahci->ahci; ahci = &sysahci->ahci;
@ -484,16 +481,16 @@ static void create_ahci(const SBSAMachineState *sms, qemu_irq *pic)
} }
} }
static void create_ehci(const SBSAMachineState *sms, qemu_irq *pic) static void create_ehci(const SBSAMachineState *sms)
{ {
hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
int irq = sbsa_ref_irqmap[SBSA_EHCI]; int irq = sbsa_ref_irqmap[SBSA_EHCI];
sysbus_create_simple("platform-ehci-usb", base, pic[irq]); sysbus_create_simple("platform-ehci-usb", base,
qdev_get_gpio_in(sms->gic, irq));
} }
static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic, static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
PCIBus *bus)
{ {
hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base; hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
int irq = sbsa_ref_irqmap[SBSA_SMMU]; int irq = sbsa_ref_irqmap[SBSA_SMMU];
@ -507,11 +504,12 @@ static void create_smmu(const SBSAMachineState *sms, qemu_irq *pic,
qdev_init_nofail(dev); qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
for (i = 0; i < NUM_SMMU_IRQS; i++) { for (i = 0; i < NUM_SMMU_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
qdev_get_gpio_in(sms->gic, irq + 1));
} }
} }
static void create_pcie(SBSAMachineState *sms, qemu_irq *pic) static void create_pcie(SBSAMachineState *sms)
{ {
hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base; hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size; hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
@ -555,7 +553,8 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
for (i = 0; i < GPEX_NUM_IRQS; i++) { for (i = 0; i < GPEX_NUM_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
qdev_get_gpio_in(sms->gic, irq + 1));
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
} }
@ -574,7 +573,7 @@ static void create_pcie(SBSAMachineState *sms, qemu_irq *pic)
pci_create_simple(pci->bus, -1, "VGA"); pci_create_simple(pci->bus, -1, "VGA");
create_smmu(sms, pic, pci->bus); create_smmu(sms, pci->bus);
} }
static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size) static void *sbsa_ref_dtb(const struct arm_boot_info *binfo, int *fdt_size)
@ -598,7 +597,6 @@ static void sbsa_ref_init(MachineState *machine)
bool firmware_loaded; bool firmware_loaded;
const CPUArchIdList *possible_cpus; const CPUArchIdList *possible_cpus;
int n, sbsa_max_cpus; int n, sbsa_max_cpus;
qemu_irq pic[NUM_IRQS];
if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
error_report("sbsa-ref: CPU type other than the built-in " error_report("sbsa-ref: CPU type other than the built-in "
@ -695,22 +693,22 @@ static void sbsa_ref_init(MachineState *machine)
create_secure_ram(sms, secure_sysmem); create_secure_ram(sms, secure_sysmem);
create_gic(sms, pic); create_gic(sms);
create_uart(sms, pic, SBSA_UART, sysmem, serial_hd(0)); create_uart(sms, SBSA_UART, sysmem, serial_hd(0));
create_uart(sms, pic, SBSA_SECURE_UART, secure_sysmem, serial_hd(1)); create_uart(sms, SBSA_SECURE_UART, secure_sysmem, serial_hd(1));
/* Second secure UART for RAS and MM from EL0 */ /* Second secure UART for RAS and MM from EL0 */
create_uart(sms, pic, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2)); create_uart(sms, SBSA_SECURE_UART_MM, secure_sysmem, serial_hd(2));
create_rtc(sms, pic); create_rtc(sms);
create_gpio(sms, pic); create_gpio(sms);
create_ahci(sms, pic); create_ahci(sms);
create_ehci(sms, pic); create_ehci(sms);
create_pcie(sms, pic); create_pcie(sms);
sms->bootinfo.ram_size = machine->ram_size; sms->bootinfo.ram_size = machine->ram_size;
sms->bootinfo.nb_cpus = smp_cpus; sms->bootinfo.nb_cpus = smp_cpus;