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target/arm: Convert conditional branch insns to decodetree 

Convert the immediate conditional branch insn B.cond to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230512144106.3608981-17-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-05-12 15:41:02 +01:00
parent e505828d30
commit 484df362dd
2 changed files with 8 additions and 24 deletions
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2
target/arm/tcg/a64.decode
View File

@ -124,3 +124,5 @@ CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
&tbz rt imm nz bitpos &tbz rt imm nz bitpos
TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19 TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
B_cond 0101010 0 ................... 0 cond:4 imm=%imm19

30
target/arm/tcg/translate-a64.c
View File

@ -1371,36 +1371,21 @@ static bool trans_TBZ(DisasContext *s, arg_tbz *a)
return true; return true;
} }
/* Conditional branch (immediate) static bool trans_B_cond(DisasContext *s, arg_B_cond *a)
* 31 25 24 23 5 4 3 0
* +---------------+----+---------------------+----+------+
* | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
* +---------------+----+---------------------+----+------+
*/
static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
{ {
unsigned int cond;
int64_t diff;
if ((insn & (1 << 4)) || (insn & (1 << 24))) {
unallocated_encoding(s);
return;
}
diff = sextract32(insn, 5, 19) * 4;
cond = extract32(insn, 0, 4);
reset_btype(s); reset_btype(s);
if (cond < 0x0e) { if (a->cond < 0x0e) {
/* genuinely conditional branches */ /* genuinely conditional branches */
DisasLabel match = gen_disas_label(s); DisasLabel match = gen_disas_label(s);
arm_gen_test_cc(cond, match.label); arm_gen_test_cc(a->cond, match.label);
gen_goto_tb(s, 0, 4); gen_goto_tb(s, 0, 4);
set_disas_label(s, match); set_disas_label(s, match);
gen_goto_tb(s, 1, diff); gen_goto_tb(s, 1, a->imm);
} else { } else {
/* 0xe and 0xf are both "always" conditions */ /* 0xe and 0xf are both "always" conditions */
gen_goto_tb(s, 0, diff); gen_goto_tb(s, 0, a->imm);
} }
return true;
} }
/* HINT instruction group, including various allocated HINTs */ /* HINT instruction group, including various allocated HINTs */
@ -2385,9 +2370,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
static void disas_b_exc_sys(DisasContext *s, uint32_t insn) static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
{ {
switch (extract32(insn, 25, 7)) { switch (extract32(insn, 25, 7)) {
case 0x2a: /* Conditional branch (immediate) */
disas_cond_b_imm(s, insn);
break;
case 0x6a: /* Exception generation / System */ case 0x6a: /* Exception generation / System */
if (insn & (1 << 24)) { if (insn & (1 << 24)) {
if (extract32(insn, 22, 2) == 0) { if (extract32(insn, 22, 2) == 0) {