mirror of https://github.com/xemu-project/xemu.git
target/arm: Move ap_to_tw_prot etc to ptw.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-23-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -10537,83 +10537,6 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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}
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}
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/* Translate section/page access permissions to page
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* R/W protection flags
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*
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* @env: CPUARMState
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* @mmu_idx: MMU index indicating required translation regime
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* @ap: The 3-bit access permissions (AP[2:0])
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* @domain_prot: The 2-bit domain access permissions
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*/
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int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_prot)
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{
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bool is_user = regime_is_user(env, mmu_idx);
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if (domain_prot == 3) {
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return PAGE_READ | PAGE_WRITE;
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}
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switch (ap) {
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case 0:
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if (arm_feature(env, ARM_FEATURE_V7)) {
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return 0;
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}
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switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
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case SCTLR_S:
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return is_user ? 0 : PAGE_READ;
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case SCTLR_R:
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return PAGE_READ;
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default:
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return 0;
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}
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case 1:
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return is_user ? 0 : PAGE_READ | PAGE_WRITE;
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case 2:
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if (is_user) {
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return PAGE_READ;
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} else {
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return PAGE_READ | PAGE_WRITE;
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}
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case 3:
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return PAGE_READ | PAGE_WRITE;
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case 4: /* Reserved. */
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return 0;
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case 5:
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return is_user ? 0 : PAGE_READ;
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case 6:
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return PAGE_READ;
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case 7:
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if (!arm_feature(env, ARM_FEATURE_V6K)) {
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return 0;
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}
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return PAGE_READ;
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default:
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g_assert_not_reached();
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}
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}
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/* Translate section/page access permissions to page
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* R/W protection flags.
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*
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* @ap: The 2-bit simple AP (AP[2:1])
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* @is_user: TRUE if accessing from PL0
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*/
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int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
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{
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switch (ap) {
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case 0:
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return is_user ? 0 : PAGE_READ | PAGE_WRITE;
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case 1:
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return PAGE_READ | PAGE_WRITE;
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case 2:
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return is_user ? 0 : PAGE_READ;
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case 3:
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return PAGE_READ;
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default:
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g_assert_not_reached();
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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#endif /* !CONFIG_USER_ONLY */
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int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
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int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
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@ -211,6 +211,87 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
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return true;
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return true;
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}
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}
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/*
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* Translate section/page access permissions to page R/W protection flags
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* @env: CPUARMState
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* @mmu_idx: MMU index indicating required translation regime
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* @ap: The 3-bit access permissions (AP[2:0])
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* @domain_prot: The 2-bit domain access permissions
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*/
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static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
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int ap, int domain_prot)
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{
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bool is_user = regime_is_user(env, mmu_idx);
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if (domain_prot == 3) {
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return PAGE_READ | PAGE_WRITE;
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}
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switch (ap) {
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case 0:
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if (arm_feature(env, ARM_FEATURE_V7)) {
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return 0;
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}
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switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
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case SCTLR_S:
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return is_user ? 0 : PAGE_READ;
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case SCTLR_R:
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return PAGE_READ;
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default:
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return 0;
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}
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case 1:
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return is_user ? 0 : PAGE_READ | PAGE_WRITE;
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case 2:
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if (is_user) {
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return PAGE_READ;
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} else {
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return PAGE_READ | PAGE_WRITE;
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}
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case 3:
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return PAGE_READ | PAGE_WRITE;
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case 4: /* Reserved. */
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return 0;
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case 5:
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return is_user ? 0 : PAGE_READ;
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case 6:
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return PAGE_READ;
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case 7:
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if (!arm_feature(env, ARM_FEATURE_V6K)) {
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return 0;
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}
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return PAGE_READ;
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default:
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g_assert_not_reached();
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}
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}
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/*
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* Translate section/page access permissions to page R/W protection flags.
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* @ap: The 2-bit simple AP (AP[2:1])
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* @is_user: TRUE if accessing from PL0
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*/
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static int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
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{
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switch (ap) {
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case 0:
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return is_user ? 0 : PAGE_READ | PAGE_WRITE;
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case 1:
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return PAGE_READ | PAGE_WRITE;
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case 2:
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return is_user ? 0 : PAGE_READ;
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case 3:
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return PAGE_READ;
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default:
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g_assert_not_reached();
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}
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}
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static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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{
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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}
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static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
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static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, int *prot,
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hwaddr *phys_ptr, int *prot,
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@ -15,15 +15,5 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx);
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bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx);
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bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx);
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uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn);
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uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn);
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int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
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int ap, int domain_prot);
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int simple_ap_to_rw_prot_is_user(int ap, bool is_user);
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static inline int
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simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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{
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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}
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#endif /* !CONFIG_USER_ONLY */
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#endif /* !CONFIG_USER_ONLY */
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#endif /* TARGET_ARM_PTW_H */
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#endif /* TARGET_ARM_PTW_H */
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