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qemu/atomic128: Add x86_64 atomic128-ldst.h
With CPUINFO_ATOMIC_VMOVDQA, we can perform proper atomic load/store without cmpxchg16b. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Load/store for 128-bit atomic operations, x86_64 version.
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*
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* Copyright (C) 2023 Linaro, Ltd.
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*
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* See docs/devel/atomics.rst for discussion about the guarantees each
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* atomic primitive is meant to provide.
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*/
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#ifndef AARCH64_ATOMIC128_LDST_H
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#define AARCH64_ATOMIC128_LDST_H
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#ifdef CONFIG_INT128_TYPE
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#include "host/cpuinfo.h"
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#include "tcg/debug-assert.h"
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/*
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* Through clang 16, with -mcx16, __atomic_load_n is incorrectly
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* expanded to a read-write operation: lock cmpxchg16b.
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*/
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#define HAVE_ATOMIC128_RO likely(cpuinfo & CPUINFO_ATOMIC_VMOVDQA)
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#define HAVE_ATOMIC128_RW 1
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static inline Int128 atomic16_read_ro(const Int128 *ptr)
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{
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Int128Alias r;
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tcg_debug_assert(HAVE_ATOMIC128_RO);
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asm("vmovdqa %1, %0" : "=x" (r.i) : "m" (*ptr));
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return r.s;
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}
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static inline Int128 atomic16_read_rw(Int128 *ptr)
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{
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__int128_t *ptr_align = __builtin_assume_aligned(ptr, 16);
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Int128Alias r;
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if (HAVE_ATOMIC128_RO) {
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asm("vmovdqa %1, %0" : "=x" (r.i) : "m" (*ptr_align));
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} else {
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r.i = __sync_val_compare_and_swap_16(ptr_align, 0, 0);
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}
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return r.s;
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}
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static inline void atomic16_set(Int128 *ptr, Int128 val)
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{
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__int128_t *ptr_align = __builtin_assume_aligned(ptr, 16);
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Int128Alias new = { .s = val };
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if (HAVE_ATOMIC128_RO) {
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asm("vmovdqa %1, %0" : "=m"(*ptr_align) : "x" (new.i));
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} else {
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__int128_t old;
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do {
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old = *ptr_align;
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} while (!__sync_bool_compare_and_swap_16(ptr_align, old, new.i));
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}
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}
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#else
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/* Provide QEMU_ERROR stubs. */
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#include "host/include/generic/host/atomic128-ldst.h"
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#endif
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#endif /* AARCH64_ATOMIC128_LDST_H */
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