From 48006e03d5425b924af31091bc28e35619ffb948 Mon Sep 17 00:00:00 2001 From: Ani Sinha Date: Mon, 31 Jan 2022 17:50:01 +0530 Subject: [PATCH 01/25] MAINTAINERS: Adding myself as a reviewer of some components MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added myself as a reviewer of vmgenid, unimplemented device and empty slot. Signed-off-by: Ani Sinha Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220131122001.1476101-1-ani@anisinha.ca Signed-off-by: Peter Maydell --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 81aa31b5e1..bd85e27889 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2189,6 +2189,7 @@ F: tests/qtest/prom-env-test.c VM Generation ID S: Orphan +R: Ani Sinha F: hw/acpi/vmgenid.c F: include/hw/acpi/vmgenid.h F: docs/specs/vmgenid.txt @@ -2204,6 +2205,7 @@ F: hw/misc/led.c Unimplemented device M: Peter Maydell R: Philippe Mathieu-Daudé +R: Ani Sinha S: Maintained F: include/hw/misc/unimp.h F: hw/misc/unimp.c @@ -2211,6 +2213,7 @@ F: hw/misc/unimp.c Empty slot M: Artyom Tarasenko R: Philippe Mathieu-Daudé +R: Ani Sinha S: Maintained F: include/hw/misc/empty_slot.h F: hw/misc/empty_slot.c From ad99f64f1cfff7c5e7af0e697523d9b7e45423b6 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 9 Feb 2022 13:41:34 +0100 Subject: [PATCH 02/25] hvf: arm: Use macros for sysreg shift/masking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are parsing the syndrome field for sysregs in multiple places across the hvf code, but repeat shift/mask operations with hard coded constants every time. This is an error prone approach and makes it harder to reason about the correctness of these operations. Let's introduce macros that allow us to unify the constants used as well as create new helpers to extract fields from the sysreg value. Suggested-by: Peter Maydell Signed-off-by: Alexander Graf Reviewed-by: Cameron Esfahani > Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220209124135.69183-1-agraf@csgraf.de Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 69 ++++++++++++++++++++++++++++++-------------- 1 file changed, 47 insertions(+), 22 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 0dc96560d3..808c96da8c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -35,9 +35,34 @@ ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) #define PL1_WRITE_MASK 0x4 +#define SYSREG_OP0_SHIFT 20 +#define SYSREG_OP0_MASK 0x3 +#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK) +#define SYSREG_OP1_SHIFT 14 +#define SYSREG_OP1_MASK 0x7 +#define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK) +#define SYSREG_CRN_SHIFT 10 +#define SYSREG_CRN_MASK 0xf +#define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK) +#define SYSREG_CRM_SHIFT 1 +#define SYSREG_CRM_MASK 0xf +#define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK) +#define SYSREG_OP2_SHIFT 17 +#define SYSREG_OP2_MASK 0x7 +#define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK) + #define SYSREG(op0, op1, crn, crm, op2) \ - ((op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (crm << 1)) -#define SYSREG_MASK SYSREG(0x3, 0x7, 0xf, 0xf, 0x7) + ((op0 << SYSREG_OP0_SHIFT) | \ + (op1 << SYSREG_OP1_SHIFT) | \ + (crn << SYSREG_CRN_SHIFT) | \ + (crm << SYSREG_CRM_SHIFT) | \ + (op2 << SYSREG_OP2_SHIFT)) +#define SYSREG_MASK \ + SYSREG(SYSREG_OP0_MASK, \ + SYSREG_OP1_MASK, \ + SYSREG_CRN_MASK, \ + SYSREG_CRM_MASK, \ + SYSREG_OP2_MASK) #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4) #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4) #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4) @@ -783,21 +808,21 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) default: cpu_synchronize_state(cpu); trace_hvf_unhandled_sysreg_read(env->pc, reg, - (reg >> 20) & 0x3, - (reg >> 14) & 0x7, - (reg >> 10) & 0xf, - (reg >> 1) & 0xf, - (reg >> 17) & 0x7); + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); return 1; } trace_hvf_sysreg_read(reg, - (reg >> 20) & 0x3, - (reg >> 14) & 0x7, - (reg >> 10) & 0xf, - (reg >> 1) & 0xf, - (reg >> 17) & 0x7, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg), val); hvf_set_reg(cpu, rt, val); @@ -886,11 +911,11 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) CPUARMState *env = &arm_cpu->env; trace_hvf_sysreg_write(reg, - (reg >> 20) & 0x3, - (reg >> 14) & 0x7, - (reg >> 10) & 0xf, - (reg >> 1) & 0xf, - (reg >> 17) & 0x7, + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg), val); switch (reg) { @@ -960,11 +985,11 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) default: cpu_synchronize_state(cpu); trace_hvf_unhandled_sysreg_write(env->pc, reg, - (reg >> 20) & 0x3, - (reg >> 14) & 0x7, - (reg >> 10) & 0xf, - (reg >> 1) & 0xf, - (reg >> 17) & 0x7); + SYSREG_OP0(reg), + SYSREG_OP1(reg), + SYSREG_CRN(reg), + SYSREG_CRM(reg), + SYSREG_OP2(reg)); hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); return 1; } From 7f6c295cdfeaa229c360cac9a36e4e595aa902ae Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 9 Feb 2022 13:41:35 +0100 Subject: [PATCH 03/25] hvf: arm: Handle unknown ID registers as RES0 Recent Linux versions added support to read ID_AA64ISAR2_EL1. On M1, those reads trap into QEMU which handles them as faults. However, AArch64 ID registers should always read as RES0. Let's handle them accordingly. This fixes booting Linux 5.17 guests. Cc: qemu-stable@nongnu.org Reported-by: Ivan Babrou Signed-off-by: Alexander Graf Message-id: 20220209124135.69183-2-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 808c96da8c..4d4ddab348 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -754,6 +754,15 @@ static bool hvf_handle_psci_call(CPUState *cpu) return true; } +static bool is_id_sysreg(uint32_t reg) +{ + return SYSREG_OP0(reg) == 3 && + SYSREG_OP1(reg) == 0 && + SYSREG_CRN(reg) == 0 && + SYSREG_CRM(reg) >= 1 && + SYSREG_CRM(reg) < 8; +} + static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -806,6 +815,11 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) /* Dummy register */ break; default: + if (is_id_sysreg(reg)) { + /* ID system registers read as RES0 */ + val = 0; + break; + } cpu_synchronize_state(cpu); trace_hvf_unhandled_sysreg_read(env->pc, reg, SYSREG_OP0(reg), From 5e78c98b7cc98619d2740c7c5030aa56fb22e79f Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Mon, 17 Jan 2022 15:58:04 +0100 Subject: [PATCH 04/25] Mark remaining global TypeInfo instances as const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit More than 1k of TypeInfo instances are already marked as const. Mark the remaining ones, too. This commit was created with: git grep -z -l 'static TypeInfo' -- '*.c' | \ xargs -0 sed -i 's/static TypeInfo/static const TypeInfo/' Signed-off-by: Bernhard Beschow Reviewed-by: Alistair Francis Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Igor Mammedov Acked-by: Corey Minyard Message-id: 20220117145805.173070-2-shentey@gmail.com Signed-off-by: Peter Maydell --- hw/core/generic-loader.c | 2 +- hw/core/guest-loader.c | 2 +- hw/display/bcm2835_fb.c | 2 +- hw/display/i2c-ddc.c | 2 +- hw/display/macfb.c | 4 ++-- hw/display/virtio-vga.c | 2 +- hw/dma/bcm2835_dma.c | 2 +- hw/i386/pc_piix.c | 2 +- hw/i386/sgx-epc.c | 2 +- hw/intc/bcm2835_ic.c | 2 +- hw/intc/bcm2836_control.c | 2 +- hw/ipmi/ipmi.c | 4 ++-- hw/mem/nvdimm.c | 2 +- hw/mem/pc-dimm.c | 2 +- hw/misc/bcm2835_mbox.c | 2 +- hw/misc/bcm2835_powermgt.c | 2 +- hw/misc/bcm2835_property.c | 2 +- hw/misc/bcm2835_rng.c | 2 +- hw/misc/pvpanic-isa.c | 2 +- hw/misc/pvpanic-pci.c | 2 +- hw/net/fsl_etsec/etsec.c | 2 +- hw/ppc/prep_systemio.c | 2 +- hw/ppc/spapr_iommu.c | 2 +- hw/s390x/s390-pci-bus.c | 2 +- hw/s390x/sclp.c | 2 +- hw/s390x/tod-kvm.c | 2 +- hw/s390x/tod-tcg.c | 2 +- hw/s390x/tod.c | 2 +- hw/scsi/lsi53c895a.c | 2 +- hw/sd/allwinner-sdhost.c | 2 +- hw/sd/aspeed_sdhci.c | 2 +- hw/sd/bcm2835_sdhost.c | 2 +- hw/sd/cadence_sdhci.c | 2 +- hw/sd/npcm7xx_sdhci.c | 2 +- hw/usb/dev-mtp.c | 2 +- hw/usb/host-libusb.c | 2 +- hw/vfio/igd.c | 2 +- hw/virtio/virtio-pmem.c | 2 +- qom/object.c | 4 ++-- 39 files changed, 42 insertions(+), 42 deletions(-) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index 504ed7ca72..c666545aa0 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -207,7 +207,7 @@ static void generic_loader_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_MISC, dc->categories); } -static TypeInfo generic_loader_info = { +static const TypeInfo generic_loader_info = { .name = TYPE_GENERIC_LOADER, .parent = TYPE_DEVICE, .instance_size = sizeof(GenericLoaderState), diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c index d3f9d1a06e..391c875a29 100644 --- a/hw/core/guest-loader.c +++ b/hw/core/guest-loader.c @@ -129,7 +129,7 @@ static void guest_loader_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_MISC, dc->categories); } -static TypeInfo guest_loader_info = { +static const TypeInfo guest_loader_info = { .name = TYPE_GUEST_LOADER, .parent = TYPE_DEVICE, .instance_size = sizeof(GuestLoaderState), diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c index 2be77bdd3a..088fc3d51c 100644 --- a/hw/display/bcm2835_fb.c +++ b/hw/display/bcm2835_fb.c @@ -454,7 +454,7 @@ static void bcm2835_fb_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_fb; } -static TypeInfo bcm2835_fb_info = { +static const TypeInfo bcm2835_fb_info = { .name = TYPE_BCM2835_FB, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835FBState), diff --git a/hw/display/i2c-ddc.c b/hw/display/i2c-ddc.c index 13eb529fc1..146489518c 100644 --- a/hw/display/i2c-ddc.c +++ b/hw/display/i2c-ddc.c @@ -113,7 +113,7 @@ static void i2c_ddc_class_init(ObjectClass *oc, void *data) isc->send = i2c_ddc_tx; } -static TypeInfo i2c_ddc_info = { +static const TypeInfo i2c_ddc_info = { .name = TYPE_I2CDDC, .parent = TYPE_I2C_SLAVE, .instance_size = sizeof(I2CDDCState), diff --git a/hw/display/macfb.c b/hw/display/macfb.c index 2eeb80cc3f..c9b468c10e 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -782,14 +782,14 @@ static void macfb_nubus_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, macfb_nubus_properties); } -static TypeInfo macfb_sysbus_info = { +static const TypeInfo macfb_sysbus_info = { .name = TYPE_MACFB, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(MacfbSysBusState), .class_init = macfb_sysbus_class_init, }; -static TypeInfo macfb_nubus_info = { +static const TypeInfo macfb_nubus_info = { .name = TYPE_NUBUS_MACFB, .parent = TYPE_NUBUS_DEVICE, .instance_size = sizeof(MacfbNubusState), diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c index b23a75a04b..5a2f7a4540 100644 --- a/hw/display/virtio-vga.c +++ b/hw/display/virtio-vga.c @@ -220,7 +220,7 @@ static void virtio_vga_base_class_init(ObjectClass *klass, void *data) virtio_vga_set_big_endian_fb); } -static TypeInfo virtio_vga_base_info = { +static const TypeInfo virtio_vga_base_info = { .name = TYPE_VIRTIO_VGA_BASE, .parent = TYPE_VIRTIO_PCI, .instance_size = sizeof(VirtIOVGABase), diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c index eb0002a2b9..5e9306110d 100644 --- a/hw/dma/bcm2835_dma.c +++ b/hw/dma/bcm2835_dma.c @@ -394,7 +394,7 @@ static void bcm2835_dma_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_dma; } -static TypeInfo bcm2835_dma_info = { +static const TypeInfo bcm2835_dma_info = { .name = TYPE_BCM2835_DMA, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835DMAState), diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index d9b344248d..8d33cf689d 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -867,7 +867,7 @@ static void isa_bridge_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_BRIDGE_ISA; }; -static TypeInfo isa_bridge_info = { +static const TypeInfo isa_bridge_info = { .name = "igd-passthrough-isa-bridge", .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCIDevice), diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c index 96b2940d75..d664829d35 100644 --- a/hw/i386/sgx-epc.c +++ b/hw/i386/sgx-epc.c @@ -167,7 +167,7 @@ static void sgx_epc_class_init(ObjectClass *oc, void *data) mdc->fill_device_info = sgx_epc_md_fill_device_info; } -static TypeInfo sgx_epc_info = { +static const TypeInfo sgx_epc_info = { .name = TYPE_SGX_EPC, .parent = TYPE_DEVICE, .instance_size = sizeof(SGXEPCDevice), diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c index 9000d995e8..4513fad16f 100644 --- a/hw/intc/bcm2835_ic.c +++ b/hw/intc/bcm2835_ic.c @@ -227,7 +227,7 @@ static void bcm2835_ic_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_ic; } -static TypeInfo bcm2835_ic_info = { +static const TypeInfo bcm2835_ic_info = { .name = TYPE_BCM2835_IC, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835ICState), diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c index 2ead76ffdc..b0589df188 100644 --- a/hw/intc/bcm2836_control.c +++ b/hw/intc/bcm2836_control.c @@ -392,7 +392,7 @@ static void bcm2836_control_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2836_control; } -static TypeInfo bcm2836_control_info = { +static const TypeInfo bcm2836_control_info = { .name = TYPE_BCM2836_CONTROL, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2836ControlState), diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c index 8d35c9fdd6..bbb07b151e 100644 --- a/hw/ipmi/ipmi.c +++ b/hw/ipmi/ipmi.c @@ -85,7 +85,7 @@ static void ipmi_interface_class_init(ObjectClass *class, void *data) ik->do_hw_op = ipmi_do_hw_op; } -static TypeInfo ipmi_interface_type_info = { +static const TypeInfo ipmi_interface_type_info = { .name = TYPE_IPMI_INTERFACE, .parent = TYPE_INTERFACE, .class_size = sizeof(IPMIInterfaceClass), @@ -120,7 +120,7 @@ static void bmc_class_init(ObjectClass *oc, void *data) device_class_set_props(dc, ipmi_bmc_properties); } -static TypeInfo ipmi_bmc_type_info = { +static const TypeInfo ipmi_bmc_type_info = { .name = TYPE_IPMI_BMC, .parent = TYPE_DEVICE, .instance_size = sizeof(IPMIBmc), diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c index 59959d5563..7c7d777781 100644 --- a/hw/mem/nvdimm.c +++ b/hw/mem/nvdimm.c @@ -264,7 +264,7 @@ static void nvdimm_class_init(ObjectClass *oc, void *data) set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } -static TypeInfo nvdimm_info = { +static const TypeInfo nvdimm_info = { .name = TYPE_NVDIMM, .parent = TYPE_PC_DIMM, .class_size = sizeof(NVDIMMClass), diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c index 03bd0dd60e..f27e1a11ba 100644 --- a/hw/mem/pc-dimm.c +++ b/hw/mem/pc-dimm.c @@ -291,7 +291,7 @@ static void pc_dimm_class_init(ObjectClass *oc, void *data) mdc->fill_device_info = pc_dimm_md_fill_device_info; } -static TypeInfo pc_dimm_info = { +static const TypeInfo pc_dimm_info = { .name = TYPE_PC_DIMM, .parent = TYPE_DEVICE, .instance_size = sizeof(PCDIMMDevice), diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c index 04e53c9828..1e4e061bc1 100644 --- a/hw/misc/bcm2835_mbox.c +++ b/hw/misc/bcm2835_mbox.c @@ -323,7 +323,7 @@ static void bcm2835_mbox_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_mbox; } -static TypeInfo bcm2835_mbox_info = { +static const TypeInfo bcm2835_mbox_info = { .name = TYPE_BCM2835_MBOX, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835MboxState), diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c index 25fa804cbd..976f3d34e5 100644 --- a/hw/misc/bcm2835_powermgt.c +++ b/hw/misc/bcm2835_powermgt.c @@ -144,7 +144,7 @@ static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_powermgt; } -static TypeInfo bcm2835_powermgt_info = { +static const TypeInfo bcm2835_powermgt_info = { .name = TYPE_BCM2835_POWERMGT, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835PowerMgtState), diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 76ea511d53..e94e951057 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -421,7 +421,7 @@ static void bcm2835_property_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_property; } -static TypeInfo bcm2835_property_info = { +static const TypeInfo bcm2835_property_info = { .name = TYPE_BCM2835_PROPERTY, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835PropertyState), diff --git a/hw/misc/bcm2835_rng.c b/hw/misc/bcm2835_rng.c index d0c4e64e88..b3c80cf186 100644 --- a/hw/misc/bcm2835_rng.c +++ b/hw/misc/bcm2835_rng.c @@ -131,7 +131,7 @@ static void bcm2835_rng_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_rng; } -static TypeInfo bcm2835_rng_info = { +static const TypeInfo bcm2835_rng_info = { .name = TYPE_BCM2835_RNG, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835RngState), diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c index 7b66d58acc..a39fcdd1fc 100644 --- a/hw/misc/pvpanic-isa.c +++ b/hw/misc/pvpanic-isa.c @@ -77,7 +77,7 @@ static void pvpanic_isa_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_MISC, dc->categories); } -static TypeInfo pvpanic_isa_info = { +static const TypeInfo pvpanic_isa_info = { .name = TYPE_PVPANIC_ISA_DEVICE, .parent = TYPE_ISA_DEVICE, .instance_size = sizeof(PVPanicISAState), diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c index af8cbe2830..62e1be68c1 100644 --- a/hw/misc/pvpanic-pci.c +++ b/hw/misc/pvpanic-pci.c @@ -74,7 +74,7 @@ static void pvpanic_pci_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_MISC, dc->categories); } -static TypeInfo pvpanic_pci_info = { +static const TypeInfo pvpanic_pci_info = { .name = TYPE_PVPANIC_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PVPanicPCIState), diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index bd9d62b559..e7fc082518 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -430,7 +430,7 @@ static void etsec_class_init(ObjectClass *klass, void *data) dc->user_creatable = true; } -static TypeInfo etsec_info = { +static const TypeInfo etsec_info = { .name = TYPE_ETSEC_COMMON, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(eTSEC), diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c index b2bd783248..8c9b8dd67b 100644 --- a/hw/ppc/prep_systemio.c +++ b/hw/ppc/prep_systemio.c @@ -300,7 +300,7 @@ static void prep_systemio_class_initfn(ObjectClass *klass, void *data) device_class_set_props(dc, prep_systemio_properties); } -static TypeInfo prep_systemio800_info = { +static const TypeInfo prep_systemio800_info = { .name = TYPE_PREP_SYSTEMIO, .parent = TYPE_ISA_DEVICE, .instance_size = sizeof(PrepSystemIoState), diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index db01071858..81e5a1aea3 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -685,7 +685,7 @@ static void spapr_tce_table_class_init(ObjectClass *klass, void *data) spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); } -static TypeInfo spapr_tce_table_info = { +static const TypeInfo spapr_tce_table_info = { .name = TYPE_SPAPR_TCE_TABLE, .parent = TYPE_DEVICE, .instance_size = sizeof(SpaprTceTable), diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 01b58ebc70..4b2bdd94b3 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -1392,7 +1392,7 @@ static const TypeInfo s390_pci_device_info = { .class_init = s390_pci_device_class_init, }; -static TypeInfo s390_pci_iommu_info = { +static const TypeInfo s390_pci_iommu_info = { .name = TYPE_S390_PCI_IOMMU, .parent = TYPE_OBJECT, .instance_size = sizeof(S390PCIIOMMU), diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c index 89c30a8a91..eff74479f4 100644 --- a/hw/s390x/sclp.c +++ b/hw/s390x/sclp.c @@ -460,7 +460,7 @@ static void sclp_class_init(ObjectClass *oc, void *data) sc->service_interrupt = service_interrupt; } -static TypeInfo sclp_info = { +static const TypeInfo sclp_info = { .name = TYPE_SCLP, .parent = TYPE_DEVICE, .instance_init = sclp_init, diff --git a/hw/s390x/tod-kvm.c b/hw/s390x/tod-kvm.c index ec855811ae..9d0cbfbce2 100644 --- a/hw/s390x/tod-kvm.c +++ b/hw/s390x/tod-kvm.c @@ -147,7 +147,7 @@ static void kvm_s390_tod_init(Object *obj) td->stopped = false; } -static TypeInfo kvm_s390_tod_info = { +static const TypeInfo kvm_s390_tod_info = { .name = TYPE_KVM_S390_TOD, .parent = TYPE_S390_TOD, .instance_size = sizeof(S390TODState), diff --git a/hw/s390x/tod-tcg.c b/hw/s390x/tod-tcg.c index 7646b4aa38..2d540dba65 100644 --- a/hw/s390x/tod-tcg.c +++ b/hw/s390x/tod-tcg.c @@ -73,7 +73,7 @@ static void qemu_s390_tod_init(Object *obj) } } -static TypeInfo qemu_s390_tod_info = { +static const TypeInfo qemu_s390_tod_info = { .name = TYPE_QEMU_S390_TOD, .parent = TYPE_S390_TOD, .instance_size = sizeof(S390TODState), diff --git a/hw/s390x/tod.c b/hw/s390x/tod.c index fd5a36bf24..c81b1c0338 100644 --- a/hw/s390x/tod.c +++ b/hw/s390x/tod.c @@ -123,7 +123,7 @@ static void s390_tod_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; } -static TypeInfo s390_tod_info = { +static const TypeInfo s390_tod_info = { .name = TYPE_S390_TOD, .parent = TYPE_DEVICE, .instance_size = sizeof(S390TODState), diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 4c431adb77..c8773f73f7 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -2352,7 +2352,7 @@ static void lsi53c810_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_LSI_53C810; } -static TypeInfo lsi53c810_info = { +static const TypeInfo lsi53c810_info = { .name = TYPE_LSI53C810, .parent = TYPE_LSI53C895A, .class_init = lsi53c810_class_init, diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index de5bc49e68..041e45c680 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -835,7 +835,7 @@ static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data) sc->max_desc_size = 64 * KiB; } -static TypeInfo allwinner_sdhost_info = { +static const TypeInfo allwinner_sdhost_info = { .name = TYPE_AW_SDHOST, .parent = TYPE_SYS_BUS_DEVICE, .instance_init = allwinner_sdhost_init, diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index df1bdf1fa4..be8cafd65f 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -198,7 +198,7 @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) device_class_set_props(dc, aspeed_sdhci_properties); } -static TypeInfo aspeed_sdhci_info = { +static const TypeInfo aspeed_sdhci_info = { .name = TYPE_ASPEED_SDHCI, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(AspeedSDHCIState), diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c index 088a7ac6ed..9431c35914 100644 --- a/hw/sd/bcm2835_sdhost.c +++ b/hw/sd/bcm2835_sdhost.c @@ -436,7 +436,7 @@ static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_bcm2835_sdhost; } -static TypeInfo bcm2835_sdhost_info = { +static const TypeInfo bcm2835_sdhost_info = { .name = TYPE_BCM2835_SDHOST, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(BCM2835SDHostState), diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c index 56b8bae1c3..75db34befe 100644 --- a/hw/sd/cadence_sdhci.c +++ b/hw/sd/cadence_sdhci.c @@ -175,7 +175,7 @@ static void cadence_sdhci_class_init(ObjectClass *classp, void *data) dc->vmsd = &vmstate_cadence_sdhci; } -static TypeInfo cadence_sdhci_info = { +static const TypeInfo cadence_sdhci_info = { .name = TYPE_CADENCE_SDHCI, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(CadenceSDHCIState), diff --git a/hw/sd/npcm7xx_sdhci.c b/hw/sd/npcm7xx_sdhci.c index ef503365df..b2f5b4a542 100644 --- a/hw/sd/npcm7xx_sdhci.c +++ b/hw/sd/npcm7xx_sdhci.c @@ -166,7 +166,7 @@ static void npcm7xx_sdhci_instance_init(Object *obj) TYPE_SYSBUS_SDHCI); } -static TypeInfo npcm7xx_sdhci_info = { +static const TypeInfo npcm7xx_sdhci_info = { .name = TYPE_NPCM7XX_SDHCI, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(NPCM7xxSDHCIState), diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c index c1d1694fd0..1e6ac76bef 100644 --- a/hw/usb/dev-mtp.c +++ b/hw/usb/dev-mtp.c @@ -2106,7 +2106,7 @@ static void usb_mtp_class_initfn(ObjectClass *klass, void *data) device_class_set_props(dc, mtp_properties); } -static TypeInfo mtp_info = { +static const TypeInfo mtp_info = { .name = TYPE_USB_MTP, .parent = TYPE_USB_DEVICE, .instance_size = sizeof(MTPState), diff --git a/hw/usb/host-libusb.c b/hw/usb/host-libusb.c index d0d46dd0a4..2b35cb6cdd 100644 --- a/hw/usb/host-libusb.c +++ b/hw/usb/host-libusb.c @@ -1801,7 +1801,7 @@ static void usb_host_class_initfn(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } -static TypeInfo usb_host_dev_info = { +static const TypeInfo usb_host_dev_info = { .name = TYPE_USB_HOST_DEVICE, .parent = TYPE_USB_DEVICE, .instance_size = sizeof(USBHostDevice), diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c index d4685709a3..afe3fe7efc 100644 --- a/hw/vfio/igd.c +++ b/hw/vfio/igd.c @@ -199,7 +199,7 @@ static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_BRIDGE_ISA; } -static TypeInfo vfio_pci_igd_lpc_bridge_info = { +static const TypeInfo vfio_pci_igd_lpc_bridge_info = { .name = "vfio-pci-igd-lpc-bridge", .parent = TYPE_PCI_DEVICE, .class_init = vfio_pci_igd_lpc_bridge_class_init, diff --git a/hw/virtio/virtio-pmem.c b/hw/virtio/virtio-pmem.c index d1aeb90a31..5419dca75e 100644 --- a/hw/virtio/virtio-pmem.c +++ b/hw/virtio/virtio-pmem.c @@ -182,7 +182,7 @@ static void virtio_pmem_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } -static TypeInfo virtio_pmem_info = { +static const TypeInfo virtio_pmem_info = { .name = TYPE_VIRTIO_PMEM, .parent = TYPE_VIRTIO_DEVICE, .class_size = sizeof(VirtIOPMEMClass), diff --git a/qom/object.c b/qom/object.c index 4f0677cca9..9f7a33139d 100644 --- a/qom/object.c +++ b/qom/object.c @@ -2793,13 +2793,13 @@ static void object_class_init(ObjectClass *klass, void *data) static void register_types(void) { - static TypeInfo interface_info = { + static const TypeInfo interface_info = { .name = TYPE_INTERFACE, .class_size = sizeof(InterfaceClass), .abstract = true, }; - static TypeInfo object_info = { + static const TypeInfo object_info = { .name = TYPE_OBJECT, .instance_size = sizeof(Object), .class_init = object_class_init, From 9a86e023aaa70e05ad9e5354f146c1477b5f5911 Mon Sep 17 00:00:00 2001 From: Bernhard Beschow Date: Mon, 17 Jan 2022 15:58:05 +0100 Subject: [PATCH 05/25] checkpatch: Ensure that TypeInfos are const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that all static TypeInfo instances are declared const, prevent that new non-const instances are created. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220117145805.173070-3-shentey@gmail.com Signed-off-by: Peter Maydell --- scripts/checkpatch.pl | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 5e50111060..ddd8148d87 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2882,6 +2882,7 @@ sub process { SCSIBusInfo| SCSIReqOps| Spice[A-Z][a-zA-Z0-9]*Interface| + TypeInfo| USBDesc[A-Z][a-zA-Z0-9]*| VhostOps| VMStateDescription| From dcfb1d0476559cabe45ffbfb1d7667909ab309c2 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Feb 2022 16:55:01 +0000 Subject: [PATCH 06/25] target/arm: Move '-cpu host' code to cpu64.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that KVM has dropped AArch32 host support, the 'host' CPU type is always AArch64, and we can move it to cpu64.c. This move will allow us to share code between it and '-cpu max', which should behave the same as '-cpu host' when using KVM or HVF. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: Alexander Graf Reviewed-by: Richard Henderson Message-id: 20220204165506.2846058-2-peter.maydell@linaro.org --- target/arm/cpu.c | 30 ------------------------------ target/arm/cpu64.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5a9c02a256..a4a229a65b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -39,7 +39,6 @@ #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" -#include "hvf_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" @@ -2079,31 +2078,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #endif /* CONFIG_TCG */ } -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) -static void arm_host_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - -#ifdef CONFIG_KVM - kvm_arm_set_cpu_features_from_host(cpu); - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - aarch64_add_sve_properties(obj); - aarch64_add_pauth_properties(obj); - } -#else - hvf_arm_set_cpu_features_from_host(cpu); -#endif - arm_cpu_post_init(obj); -} - -static const TypeInfo host_arm_cpu_type_info = { - .name = TYPE_ARM_HOST_CPU, - .parent = TYPE_AARCH64_CPU, - .instance_init = arm_host_initfn, -}; - -#endif - static void arm_cpu_instance_init(Object *obj) { ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); @@ -2151,10 +2125,6 @@ static const TypeInfo arm_cpu_type_info = { static void arm_cpu_register_types(void) { type_register_static(&arm_cpu_type_info); - -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - type_register_static(&host_arm_cpu_type_info); -#endif } type_init(arm_cpu_register_types) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8786be7783..052666b819 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -30,6 +30,7 @@ #endif #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" @@ -681,6 +682,31 @@ void aarch64_add_pauth_properties(Object *obj) } } +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +static void arm_host_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + +#ifdef CONFIG_KVM + kvm_arm_set_cpu_features_from_host(cpu); + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + aarch64_add_sve_properties(obj); + aarch64_add_pauth_properties(obj); + } +#else + hvf_arm_set_cpu_features_from_host(cpu); +#endif + arm_cpu_post_init(obj); +} + +static const TypeInfo host_arm_cpu_type_info = { + .name = TYPE_ARM_HOST_CPU, + .parent = TYPE_AARCH64_CPU, + .instance_init = arm_host_initfn, +}; + +#endif + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -1023,6 +1049,10 @@ static void aarch64_cpu_register_types(void) for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { aarch64_cpu_register(&aarch64_cpus[i]); } + +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + type_register_static(&host_arm_cpu_type_info); +#endif } type_init(aarch64_cpu_register_types) From 73cc9ee6bfadcdbd079cf4871179ef5760146d1c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Feb 2022 16:55:02 +0000 Subject: [PATCH 07/25] target/arm: Use aarch64_cpu_register() for 'host' CPU type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the aarch64_cpu_register() machinery to register the 'host' CPU type. This doesn't gain us anything functionally, but it does mean that the code for initializing it looks more like that for the other CPU types, in that its initfn then doesn't need to call arm_cpu_post_init() (because aarch64_cpu_instance_init() does that for it). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: Alexander Graf Reviewed-by: Richard Henderson Message-id: 20220204165506.2846058-3-peter.maydell@linaro.org --- target/arm/cpu64.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 052666b819..590ac56271 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -683,7 +683,7 @@ void aarch64_add_pauth_properties(Object *obj) } #if defined(CONFIG_KVM) || defined(CONFIG_HVF) -static void arm_host_initfn(Object *obj) +static void aarch64_host_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -696,15 +696,7 @@ static void arm_host_initfn(Object *obj) #else hvf_arm_set_cpu_features_from_host(cpu); #endif - arm_cpu_post_init(obj); } - -static const TypeInfo host_arm_cpu_type_info = { - .name = TYPE_ARM_HOST_CPU, - .parent = TYPE_AARCH64_CPU, - .instance_init = arm_host_initfn, -}; - #endif /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); @@ -943,6 +935,9 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) + { .name = "host", .initfn = aarch64_host_initfn }, +#endif }; static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) @@ -1049,10 +1044,6 @@ static void aarch64_cpu_register_types(void) for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { aarch64_cpu_register(&aarch64_cpus[i]); } - -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - type_register_static(&host_arm_cpu_type_info); -#endif } type_init(aarch64_cpu_register_types) From 0baa21be497ddbd8f4eea920464aaa096004733b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Feb 2022 16:55:03 +0000 Subject: [PATCH 08/25] target/arm: Make KVM -cpu max exactly like -cpu host MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently for KVM the intention is that '-cpu max' and '-cpu host' are the same thing, but because we did this with two separate pieces of code they have got a little bit out of sync. Specifically, 'max' has a 'sve-max-vq' property, and 'host' does not. Bring the two together by having the initfn for 'max' actually call the initfn for 'host'. This will result in 'max' no longer exposing the 'sve-max-vq' property when using KVM. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: Alexander Graf Reviewed-by: Richard Henderson Message-id: 20220204165506.2846058-4-peter.maydell@linaro.org --- target/arm/cpu64.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 590ac56271..ae2e431247 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -682,22 +682,22 @@ void aarch64_add_pauth_properties(Object *obj) } } -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) static void aarch64_host_initfn(Object *obj) { +#if defined(CONFIG_KVM) ARMCPU *cpu = ARM_CPU(obj); - -#ifdef CONFIG_KVM kvm_arm_set_cpu_features_from_host(cpu); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); aarch64_add_pauth_properties(obj); } -#else +#elif defined(CONFIG_HVF) + ARMCPU *cpu = ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); +#else + g_assert_not_reached(); #endif } -#endif /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. @@ -709,7 +709,9 @@ static void aarch64_max_initfn(Object *obj) ARMCPU *cpu = ARM_CPU(obj); if (kvm_enabled()) { - kvm_arm_set_cpu_features_from_host(cpu); + /* With KVM, '-cpu max' is identical to '-cpu host' */ + aarch64_host_initfn(obj); + return; } else { uint64_t t; uint32_t u; From ddaebdda53fc850d947e5983b14ae113e2bf805a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Feb 2022 16:55:04 +0000 Subject: [PATCH 09/25] target/arm: Unindent unnecessary else-clause MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that the if() branch of the condition in aarch64_max_initfn() returns early, we don't need to keep the rest of the code in the function inside an else block. Remove the else, unindenting that code. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: Alexander Graf Reviewed-by: Richard Henderson Message-id: 20220204165506.2846058-5-peter.maydell@linaro.org --- target/arm/cpu64.c | 289 +++++++++++++++++++++++---------------------- 1 file changed, 146 insertions(+), 143 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index ae2e431247..2280e476fd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -707,176 +707,179 @@ static void aarch64_host_initfn(Object *obj) static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); + uint64_t t; + uint32_t u; if (kvm_enabled()) { /* With KVM, '-cpu max' is identical to '-cpu host' */ aarch64_host_initfn(obj); return; - } else { - uint64_t t; - uint32_t u; - aarch64_a57_initfn(obj); + } - /* - * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real - * one and try to apply errata workarounds or use impdef features we - * don't provide. - * An IMPLEMENTER field of 0 means "reserved for software use"; - * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers - * to see which features are present"; - * the VARIANT, PARTNUM and REVISION fields are all implementation - * defined and we choose to define PARTNUM just in case guest - * code needs to distinguish this QEMU CPU from other software - * implementations, though this shouldn't be needed. - */ - t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); - t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); - t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); - t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); - t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); - cpu->midr = t; + /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ - t = cpu->isar.id_aa64isar0; - t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ - t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); - cpu->isar.id_aa64isar0 = t; + aarch64_a57_initfn(obj); - t = cpu->isar.id_aa64isar1; - t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); - cpu->isar.id_aa64isar1 = t; + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real + * one and try to apply errata workarounds or use impdef features we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers + * to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); + t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); + t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); + cpu->midr = t; - t = cpu->isar.id_aa64pfr0; - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); - cpu->isar.id_aa64pfr0 = t; + t = cpu->isar.id_aa64isar0; + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + cpu->isar.id_aa64isar0 = t; - t = cpu->isar.id_aa64pfr1; - t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); - /* - * Begin with full support for MTE. This will be downgraded to MTE=0 - * during realize if the board provides no tag memory, much like - * we do for EL2 with the virtualization=on property. - */ - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); - cpu->isar.id_aa64pfr1 = t; + t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + cpu->isar.id_aa64isar1 = t; - t = cpu->isar.id_aa64mmfr0; - t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ - cpu->isar.id_aa64mmfr0 = t; + t = cpu->isar.id_aa64pfr0; + t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); + t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + cpu->isar.id_aa64pfr0 = t; - t = cpu->isar.id_aa64mmfr1; - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ - cpu->isar.id_aa64mmfr1 = t; + t = cpu->isar.id_aa64pfr1; + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + /* + * Begin with full support for MTE. This will be downgraded to MTE=0 + * during realize if the board provides no tag memory, much like + * we do for EL2 with the virtualization=on property. + */ + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + cpu->isar.id_aa64pfr1 = t; - t = cpu->isar.id_aa64mmfr2; - t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - cpu->isar.id_aa64mmfr2 = t; + t = cpu->isar.id_aa64mmfr0; + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + cpu->isar.id_aa64mmfr0 = t; - t = cpu->isar.id_aa64zfr0; - t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); - cpu->isar.id_aa64zfr0 = t; + t = cpu->isar.id_aa64mmfr1; + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + cpu->isar.id_aa64mmfr1 = t; - /* Replicate the same data to the 32-bit id registers. */ - u = cpu->isar.id_isar5; - u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u = FIELD_DP32(u, ID_ISAR5, RDM, 1); - u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 = u; + t = cpu->isar.id_aa64mmfr2; + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ + cpu->isar.id_aa64mmfr2 = t; - u = cpu->isar.id_isar6; - u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u = FIELD_DP32(u, ID_ISAR6, DP, 1); - u = FIELD_DP32(u, ID_ISAR6, FHM, 1); - u = FIELD_DP32(u, ID_ISAR6, SB, 1); - u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u = FIELD_DP32(u, ID_ISAR6, BF16, 1); - u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 = u; + t = cpu->isar.id_aa64zfr0; + t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + cpu->isar.id_aa64zfr0 = t; - u = cpu->isar.id_pfr0; - u = FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 = u; + /* Replicate the same data to the 32-bit id registers. */ + u = cpu->isar.id_isar5; + u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ + u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); + u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); + u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); + u = FIELD_DP32(u, ID_ISAR5, RDM, 1); + u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 = u; - u = cpu->isar.id_pfr2; - u = FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 = u; + u = cpu->isar.id_isar6; + u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); + u = FIELD_DP32(u, ID_ISAR6, DP, 1); + u = FIELD_DP32(u, ID_ISAR6, FHM, 1); + u = FIELD_DP32(u, ID_ISAR6, SB, 1); + u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); + u = FIELD_DP32(u, ID_ISAR6, BF16, 1); + u = FIELD_DP32(u, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 = u; - u = cpu->isar.id_mmfr3; - u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 = u; + u = cpu->isar.id_pfr0; + u = FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 = u; - u = cpu->isar.id_mmfr4; - u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 = u; + u = cpu->isar.id_pfr2; + u = FIELD_DP32(u, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 = u; - t = cpu->isar.id_aa64dfr0; - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ - cpu->isar.id_aa64dfr0 = t; + u = cpu->isar.id_mmfr3; + u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 = u; - u = cpu->isar.id_dfr0; - u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 = u; + u = cpu->isar.id_mmfr4; + u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ + u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ + u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 = u; - u = cpu->isar.mvfr1; - u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 = u; + t = cpu->isar.id_aa64dfr0; + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 = t; + + u = cpu->isar.id_dfr0; + u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 = u; + + u = cpu->isar.mvfr1; + u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ + u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 = u; #ifdef CONFIG_USER_ONLY - /* For usermode -cpu max we can use a larger and more efficient DCZ - * blocksize since we don't have to follow what the hardware does. - */ - cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ - cpu->dcz_blocksize = 7; /* 512 bytes */ + /* + * For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ + cpu->dcz_blocksize = 7; /* 512 bytes */ #endif - bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); - } + bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); From 6ee609b7522b712af76225792e55596d85d8fd1f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Feb 2022 16:55:05 +0000 Subject: [PATCH 10/25] target/arm: Fix '-cpu max' for HVF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently when using hvf we mishandle '-cpu max': we fall through to the TCG version of its initfn, which then sets a lot of feature bits that the real host CPU doesn't have. The hvf accelerator code then exposes these bogus ID register values to the guest because it doesn't check that the host really has the features. Make '-cpu host' be like '-cpu max' for hvf, as we do with kvm. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: Alexander Graf Reviewed-by: Richard Henderson Message-id: 20220204165506.2846058-6-peter.maydell@linaro.org --- target/arm/cpu64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2280e476fd..19330d9ee9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,7 @@ #include "hw/loader.h" #endif #include "sysemu/kvm.h" +#include "sysemu/hvf.h" #include "kvm_arm.h" #include "hvf_arm.h" #include "qapi/visitor.h" @@ -710,8 +711,8 @@ static void aarch64_max_initfn(Object *obj) uint64_t t; uint32_t u; - if (kvm_enabled()) { - /* With KVM, '-cpu max' is identical to '-cpu host' */ + if (kvm_enabled() || hvf_enabled()) { + /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ aarch64_host_initfn(obj); return; } From 92d6528dbb20c6aec4022dfd63c7ffee44f19f77 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 4 Feb 2022 16:55:06 +0000 Subject: [PATCH 11/25] target/arm: Support PAuth extension for hvf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently we don't allow guests under hvf to use the PAuth extension, because we didn't have any special code to handle that, and therefore in arm_cpu_pauth_finalize() we will sanitize the ID_AA64ISAR1 value the guest sees to clear the PAuth related fields. Add support for this in the same way that KVM does it, by defaulting to "PAuth enabled" if the host CPU has it and allowing the user to disable it via '-cpu pauth=no' on the command line. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Andrew Jones Reviewed-by: Alexander Graf Reviewed-by: Richard Henderson Message-id: 20220204165506.2846058-7-peter.maydell@linaro.org --- target/arm/cpu64.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 19330d9ee9..1171ab16b9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -633,9 +633,10 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) uint64_t t; /* Exit early if PAuth is enabled, and fall through to disable it */ - if (kvm_enabled() && cpu->prop_pauth) { + if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { if (!cpu_isar_feature(aa64_pauth, cpu)) { - error_setg(errp, "'pauth' feature not supported by KVM on this host"); + error_setg(errp, "'pauth' feature not supported by %s on this host", + kvm_enabled() ? "KVM" : "hvf"); } return; @@ -672,10 +673,14 @@ void aarch64_add_pauth_properties(Object *obj) /* Default to PAUTH on, with the architected algorithm on TCG. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - if (kvm_enabled()) { + if (kvm_enabled() || hvf_enabled()) { /* * Mirror PAuth support from the probed sysregs back into the - * property for KVM. Is it just a bit backward? Yes it is! + * property for KVM or hvf. Is it just a bit backward? Yes it is! + * Note that prop_pauth is true whether the host CPU supports the + * architected QARMA5 algorithm or the IMPDEF one. We don't + * provide the separate pauth-impdef property for KVM or hvf, + * only for TCG. */ cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); } else { @@ -695,6 +700,7 @@ static void aarch64_host_initfn(Object *obj) #elif defined(CONFIG_HVF) ARMCPU *cpu = ARM_CPU(obj); hvf_arm_set_cpu_features_from_host(cpu); + aarch64_add_pauth_properties(obj); #else g_assert_not_reached(); #endif From b5bf5a53d1e02eb0c7fdc6271e10ebd0eda79813 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 15:59:10 +0000 Subject: [PATCH 12/25] Kconfig: Add I2C_DEVICES device group MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently there is no way for a board model's Kconfig stanza to say "I have an i2c bus which the user can plug an i2c device into, build all the free-standing i2c devices". The Kconfig mechanism for this is the "device group". Add an I2C_DEVICES group along the same lines as the existing PCI_DEVICES. Simple free-standing i2c devices which a user might plausibly want to be able to plug in on the QEMU commandline should have default y if I2C_DEVICES and board models which have an i2c bus that is user-accessible should use imply I2C_DEVICES to cause those pluggable devices to be built. In this commit we mark only a fairly conservative set of i2c devices as belonging to the I2C_DEVICES group: the simple sensors and RTCs (not including PMBus devices or devices which need GPIO lines to be connected). Signed-off-by: Peter Maydell Acked-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Hao Wu Message-id: 20220208155911.3408455-2-peter.maydell@linaro.org --- docs/devel/kconfig.rst | 8 ++++++-- hw/i2c/Kconfig | 5 +++++ hw/rtc/Kconfig | 2 ++ hw/sensor/Kconfig | 5 +++++ 4 files changed, 18 insertions(+), 2 deletions(-) diff --git a/docs/devel/kconfig.rst b/docs/devel/kconfig.rst index a1cdbec751..aa5042f156 100644 --- a/docs/devel/kconfig.rst +++ b/docs/devel/kconfig.rst @@ -192,11 +192,15 @@ declares its dependencies in different ways: no directive and are not used in the Makefile either; they only appear as conditions for ``default y`` directives. - QEMU currently has two device groups, ``PCI_DEVICES`` and - ``TEST_DEVICES``. PCI devices usually have a ``default y if + QEMU currently has three device groups, ``PCI_DEVICES``, ``I2C_DEVICES``, + and ``TEST_DEVICES``. PCI devices usually have a ``default y if PCI_DEVICES`` directive rather than just ``default y``. This lets some boards (notably s390) easily support a subset of PCI devices, for example only VFIO (passthrough) and virtio-pci devices. + ``I2C_DEVICES`` is similar to ``PCI_DEVICES``. It contains i2c devices + that users might reasonably want to plug in to an i2c bus on any + board (and not ones which are very board-specific or that need + to be wired up in a way that can't be done on the command line). ``TEST_DEVICES`` instead is used for devices that are rarely used on production virtual machines, but provide useful hooks to test QEMU or KVM. diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig index 8217cb5041..9bb8870517 100644 --- a/hw/i2c/Kconfig +++ b/hw/i2c/Kconfig @@ -1,6 +1,11 @@ config I2C bool +config I2C_DEVICES + # Device group for i2c devices which can reasonably be user-plugged + # to any board's i2c bus + bool + config SMBUS bool select I2C diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig index f06e133b8a..730c272bc5 100644 --- a/hw/rtc/Kconfig +++ b/hw/rtc/Kconfig @@ -1,10 +1,12 @@ config DS1338 bool depends on I2C + default y if I2C_DEVICES config M41T80 bool depends on I2C + default y if I2C_DEVICES config M48T59 bool diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index b317f91b7b..215944decc 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -1,18 +1,22 @@ config TMP105 bool depends on I2C + default y if I2C_DEVICES config TMP421 bool depends on I2C + default y if I2C_DEVICES config DPS310 bool depends on I2C + default y if I2C_DEVICES config EMC141X bool depends on I2C + default y if I2C_DEVICES config ADM1272 bool @@ -25,3 +29,4 @@ config MAX34451 config LSM303DLHC_MAG bool depends on I2C + default y if I2C_DEVICES From e117e9748f6946dcddfea6f157f9ab2b5f069f70 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 15:59:11 +0000 Subject: [PATCH 13/25] Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For arm boards with an i2c bus which a user could reasonably want to plug arbitrary devices, add 'imply I2C_DEVICES' to the Kconfig stanza. Signed-off-by: Peter Maydell Acked-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Hao Wu Message-id: 20220208155911.3408455-3-peter.maydell@linaro.org --- hw/arm/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2e0049196d..6945330030 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -46,6 +46,7 @@ config DIGIC config EXYNOS4 bool + imply I2C_DEVICES select A9MPCORE select I2C select LAN9118 @@ -184,6 +185,7 @@ config REALVIEW bool imply PCI_DEVICES imply PCI_TESTDEV + imply I2C_DEVICES select SMC91C111 select LAN9118 select A9MPCORE @@ -229,6 +231,7 @@ config SABRELITE config STELLARIS bool + imply I2C_DEVICES select ARM_V7M select CMSDK_APB_WATCHDOG select I2C @@ -406,6 +409,7 @@ config NPCM7XX config FSL_IMX25 bool + imply I2C_DEVICES select IMX select IMX_FEC select IMX_I2C @@ -414,6 +418,7 @@ config FSL_IMX25 config FSL_IMX31 bool + imply I2C_DEVICES select SERIAL select IMX select IMX_I2C @@ -422,6 +427,7 @@ config FSL_IMX31 config FSL_IMX6 bool + imply I2C_DEVICES select A9MPCORE select IMX select IMX_FEC @@ -450,6 +456,7 @@ config ASPEED_SOC config MPS2 bool + imply I2C_DEVICES select ARMSSE select LAN9118 select MPS2_FPGAIO @@ -466,6 +473,7 @@ config FSL_IMX7 bool imply PCI_DEVICES imply TEST_DEVICES + imply I2C_DEVICES select A15MPCORE select PCI select IMX @@ -481,6 +489,7 @@ config ARM_SMMUV3 config FSL_IMX6UL bool + imply I2C_DEVICES select A15MPCORE select IMX select IMX_FEC @@ -495,6 +504,7 @@ config MICROBIT config NRF51_SOC bool + imply I2C_DEVICES select I2C select ARM_V7M select UNIMP From 542e87c7a2d90076b07611987fd3d789865e5ea1 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 17:16:43 +0000 Subject: [PATCH 14/25] hw/arm/armv7m: Handle disconnected clock inputs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the armv7m object, handle clock inputs that aren't connected. This is always an error for 'cpuclk'. For 'refclk' it is OK for this to be disconnected, but we need to handle it by not trying to connect a sourceless-clock to the systick device. This fixes a bug where on the mps2-an521 and similar boards (which do not have a refclk) the systick device incorrectly reset with SYST_CSR.CLKSOURCE 0 ("use refclk") rather than 1 ("use CPU clock"). Cc: qemu-stable@nongnu.org Reported-by: Richard Petri Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20220208171643.3486277-1-peter.maydell@linaro.org --- hw/arm/armv7m.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index ceb76df3cd..41cfca0f22 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -284,6 +284,12 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } + /* cpuclk must be connected; refclk is optional */ + if (!clock_has_source(s->cpuclk)) { + error_setg(errp, "armv7m: cpuclk must be connected"); + return; + } + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1); s->cpu = ARM_CPU(object_new_with_props(s->cpu_type, OBJECT(s), "cpu", @@ -420,8 +426,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp) &s->sysreg_ns_mem); } - /* Create and map the systick devices */ - qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refclk); + /* + * Create and map the systick devices. Note that we only connect + * refclk if it has been connected to us; otherwise the systick + * device gets the wrong answer for clock_has_source(refclk), because + * it has an immediate source (the ARMv7M's clock object) but not + * an ultimate source, and then it won't correctly auto-select the + * CPU clock as its only possible clock source. + */ + if (clock_has_source(s->refclk)) { + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", + s->refclk); + } qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk); if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) { return; @@ -438,8 +454,10 @@ static void armv7m_realize(DeviceState *dev, Error **errp) */ object_initialize_child(OBJECT(dev), "systick-reg-s", &s->systick[M_REG_S], TYPE_SYSTICK); - qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk", - s->refclk); + if (clock_has_source(s->refclk)) { + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk", + s->refclk); + } qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk", s->cpuclk); From b85ea5fa2f0bc281b9700a51ba69aebcc76b108c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 20:08:52 +0000 Subject: [PATCH 15/25] include: Move qemu_madvise() and related #defines to new qemu/madvise.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function qemu_madvise() and the QEMU_MADV_* constants associated with it are used in only 10 files. Move them out of osdep.h to a new qemu/madvise.h header that is included where it is needed. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20220208200856.3558249-2-peter.maydell@linaro.org --- backends/hostmem-file.c | 1 + backends/hostmem.c | 1 + hw/virtio/virtio-balloon.c | 1 + include/qemu/madvise.h | 95 ++++++++++++++++++++++++++++++++++++++ include/qemu/osdep.h | 82 -------------------------------- migration/postcopy-ram.c | 1 + migration/qemu-file.c | 1 + migration/ram.c | 1 + softmmu/physmem.c | 1 + tcg/region.c | 1 + util/osdep.c | 1 + util/oslib-posix.c | 1 + 12 files changed, 105 insertions(+), 82 deletions(-) create mode 100644 include/qemu/madvise.h diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c index cd038024fa..25141283c4 100644 --- a/backends/hostmem-file.c +++ b/backends/hostmem-file.c @@ -14,6 +14,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "qemu/madvise.h" #include "sysemu/hostmem.h" #include "qom/object_interfaces.h" #include "qom/object.h" diff --git a/backends/hostmem.c b/backends/hostmem.c index 4c05862ed5..b2a5e905e8 100644 --- a/backends/hostmem.c +++ b/backends/hostmem.c @@ -19,6 +19,7 @@ #include "qemu/config-file.h" #include "qom/object_interfaces.h" #include "qemu/mmap-alloc.h" +#include "qemu/madvise.h" #ifdef CONFIG_NUMA #include diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c index 9a4f491b54..e6c1b0aa46 100644 --- a/hw/virtio/virtio-balloon.c +++ b/hw/virtio/virtio-balloon.c @@ -17,6 +17,7 @@ #include "qemu/iov.h" #include "qemu/module.h" #include "qemu/timer.h" +#include "qemu/madvise.h" #include "hw/virtio/virtio.h" #include "hw/mem/pc-dimm.h" #include "hw/qdev-properties.h" diff --git a/include/qemu/madvise.h b/include/qemu/madvise.h new file mode 100644 index 0000000000..e155f59a0d --- /dev/null +++ b/include/qemu/madvise.h @@ -0,0 +1,95 @@ +/* + * QEMU madvise wrapper functions + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_MADVISE_H +#define QEMU_MADVISE_H + +#define QEMU_MADV_INVALID -1 + +#if defined(CONFIG_MADVISE) + +#define QEMU_MADV_WILLNEED MADV_WILLNEED +#define QEMU_MADV_DONTNEED MADV_DONTNEED +#ifdef MADV_DONTFORK +#define QEMU_MADV_DONTFORK MADV_DONTFORK +#else +#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID +#endif +#ifdef MADV_MERGEABLE +#define QEMU_MADV_MERGEABLE MADV_MERGEABLE +#else +#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID +#endif +#ifdef MADV_UNMERGEABLE +#define QEMU_MADV_UNMERGEABLE MADV_UNMERGEABLE +#else +#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID +#endif +#ifdef MADV_DODUMP +#define QEMU_MADV_DODUMP MADV_DODUMP +#else +#define QEMU_MADV_DODUMP QEMU_MADV_INVALID +#endif +#ifdef MADV_DONTDUMP +#define QEMU_MADV_DONTDUMP MADV_DONTDUMP +#else +#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID +#endif +#ifdef MADV_HUGEPAGE +#define QEMU_MADV_HUGEPAGE MADV_HUGEPAGE +#else +#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID +#endif +#ifdef MADV_NOHUGEPAGE +#define QEMU_MADV_NOHUGEPAGE MADV_NOHUGEPAGE +#else +#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID +#endif +#ifdef MADV_REMOVE +#define QEMU_MADV_REMOVE MADV_REMOVE +#else +#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED +#endif +#ifdef MADV_POPULATE_WRITE +#define QEMU_MADV_POPULATE_WRITE MADV_POPULATE_WRITE +#else +#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID +#endif + +#elif defined(CONFIG_POSIX_MADVISE) + +#define QEMU_MADV_WILLNEED POSIX_MADV_WILLNEED +#define QEMU_MADV_DONTNEED POSIX_MADV_DONTNEED +#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID +#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID +#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID +#define QEMU_MADV_DODUMP QEMU_MADV_INVALID +#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID +#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID +#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID +#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED +#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID + +#else /* no-op */ + +#define QEMU_MADV_WILLNEED QEMU_MADV_INVALID +#define QEMU_MADV_DONTNEED QEMU_MADV_INVALID +#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID +#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID +#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID +#define QEMU_MADV_DODUMP QEMU_MADV_INVALID +#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID +#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID +#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID +#define QEMU_MADV_REMOVE QEMU_MADV_INVALID +#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID + +#endif + +int qemu_madvise(void *addr, size_t len, int advice); + +#endif diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index ce12f64853..5ebd737aeb 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -425,87 +425,6 @@ static inline void qemu_cleanup_generic_vfree(void *p) #define QEMU_MAP_NORESERVE (1 << 3) -#define QEMU_MADV_INVALID -1 - -#if defined(CONFIG_MADVISE) - -#define QEMU_MADV_WILLNEED MADV_WILLNEED -#define QEMU_MADV_DONTNEED MADV_DONTNEED -#ifdef MADV_DONTFORK -#define QEMU_MADV_DONTFORK MADV_DONTFORK -#else -#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID -#endif -#ifdef MADV_MERGEABLE -#define QEMU_MADV_MERGEABLE MADV_MERGEABLE -#else -#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID -#endif -#ifdef MADV_UNMERGEABLE -#define QEMU_MADV_UNMERGEABLE MADV_UNMERGEABLE -#else -#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID -#endif -#ifdef MADV_DODUMP -#define QEMU_MADV_DODUMP MADV_DODUMP -#else -#define QEMU_MADV_DODUMP QEMU_MADV_INVALID -#endif -#ifdef MADV_DONTDUMP -#define QEMU_MADV_DONTDUMP MADV_DONTDUMP -#else -#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID -#endif -#ifdef MADV_HUGEPAGE -#define QEMU_MADV_HUGEPAGE MADV_HUGEPAGE -#else -#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID -#endif -#ifdef MADV_NOHUGEPAGE -#define QEMU_MADV_NOHUGEPAGE MADV_NOHUGEPAGE -#else -#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID -#endif -#ifdef MADV_REMOVE -#define QEMU_MADV_REMOVE MADV_REMOVE -#else -#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED -#endif -#ifdef MADV_POPULATE_WRITE -#define QEMU_MADV_POPULATE_WRITE MADV_POPULATE_WRITE -#else -#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID -#endif - -#elif defined(CONFIG_POSIX_MADVISE) - -#define QEMU_MADV_WILLNEED POSIX_MADV_WILLNEED -#define QEMU_MADV_DONTNEED POSIX_MADV_DONTNEED -#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID -#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID -#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID -#define QEMU_MADV_DODUMP QEMU_MADV_INVALID -#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID -#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID -#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID -#define QEMU_MADV_REMOVE QEMU_MADV_DONTNEED -#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID - -#else /* no-op */ - -#define QEMU_MADV_WILLNEED QEMU_MADV_INVALID -#define QEMU_MADV_DONTNEED QEMU_MADV_INVALID -#define QEMU_MADV_DONTFORK QEMU_MADV_INVALID -#define QEMU_MADV_MERGEABLE QEMU_MADV_INVALID -#define QEMU_MADV_UNMERGEABLE QEMU_MADV_INVALID -#define QEMU_MADV_DODUMP QEMU_MADV_INVALID -#define QEMU_MADV_DONTDUMP QEMU_MADV_INVALID -#define QEMU_MADV_HUGEPAGE QEMU_MADV_INVALID -#define QEMU_MADV_NOHUGEPAGE QEMU_MADV_INVALID -#define QEMU_MADV_REMOVE QEMU_MADV_INVALID -#define QEMU_MADV_POPULATE_WRITE QEMU_MADV_INVALID - -#endif #ifdef _WIN32 #define HAVE_CHARDEV_SERIAL 1 @@ -577,7 +496,6 @@ void sigaction_invoke(struct sigaction *action, struct qemu_signalfd_siginfo *info); #endif -int qemu_madvise(void *addr, size_t len, int advice); int qemu_mprotect_rw(void *addr, size_t size); int qemu_mprotect_rwx(void *addr, size_t size); int qemu_mprotect_none(void *addr, size_t size); diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c index e662dd05cc..2a2cc5faf8 100644 --- a/migration/postcopy-ram.c +++ b/migration/postcopy-ram.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/rcu.h" +#include "qemu/madvise.h" #include "exec/target_page.h" #include "migration.h" #include "qemu-file.h" diff --git a/migration/qemu-file.c b/migration/qemu-file.c index 6338d8e2ff..1479cddad9 100644 --- a/migration/qemu-file.c +++ b/migration/qemu-file.c @@ -23,6 +23,7 @@ */ #include "qemu/osdep.h" #include +#include "qemu/madvise.h" #include "qemu/error-report.h" #include "qemu/iov.h" #include "migration.h" diff --git a/migration/ram.c b/migration/ram.c index 91ca743ac8..781f0745dc 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -30,6 +30,7 @@ #include "qemu/cutils.h" #include "qemu/bitops.h" #include "qemu/bitmap.h" +#include "qemu/madvise.h" #include "qemu/main-loop.h" #include "xbzrle.h" #include "ram.h" diff --git a/softmmu/physmem.c b/softmmu/physmem.c index dddf70edf5..a13289a594 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -23,6 +23,7 @@ #include "qemu/cutils.h" #include "qemu/cacheflush.h" +#include "qemu/madvise.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" diff --git a/tcg/region.c b/tcg/region.c index 9cc30d4922..c46021d160 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/madvise.h" #include "qapi/error.h" #include "exec/exec-all.h" #include "tcg/tcg.h" diff --git a/util/osdep.c b/util/osdep.c index 67fbf22778..8c5cd6e431 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -38,6 +38,7 @@ extern int madvise(char *, size_t, int); #include "qemu/cutils.h" #include "qemu/sockets.h" #include "qemu/error-report.h" +#include "qemu/madvise.h" #include "monitor/monitor.h" static bool fips_enabled = false; diff --git a/util/oslib-posix.c b/util/oslib-posix.c index ac0dbc2adc..f2be7321c5 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -36,6 +36,7 @@ #include "trace.h" #include "qapi/error.h" #include "qemu/error-report.h" +#include "qemu/madvise.h" #include "qemu/sockets.h" #include "qemu/thread.h" #include From f2241d16eaa142b4092b11ace48f2a0472bf4ad6 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 20:08:53 +0000 Subject: [PATCH 16/25] include: Move qemu_mprotect_*() to new qemu/mprotect.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The qemu_mprotect_*() family of functions are used in very few files; move them from osdep.h to a new qemu/mprotect.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20220208200856.3558249-3-peter.maydell@linaro.org --- include/qemu/mprotect.h | 14 ++++++++++++++ include/qemu/osdep.h | 4 ---- tcg/region.c | 1 + util/osdep.c | 1 + 4 files changed, 16 insertions(+), 4 deletions(-) create mode 100644 include/qemu/mprotect.h diff --git a/include/qemu/mprotect.h b/include/qemu/mprotect.h new file mode 100644 index 0000000000..1e83d1433e --- /dev/null +++ b/include/qemu/mprotect.h @@ -0,0 +1,14 @@ +/* + * QEMU mprotect functions + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef QEMU_MPROTECT_H +#define QEMU_MPROTECT_H + +int qemu_mprotect_rw(void *addr, size_t size); +int qemu_mprotect_rwx(void *addr, size_t size); +int qemu_mprotect_none(void *addr, size_t size); + +#endif diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 5ebd737aeb..ca00899bbd 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -496,10 +496,6 @@ void sigaction_invoke(struct sigaction *action, struct qemu_signalfd_siginfo *info); #endif -int qemu_mprotect_rw(void *addr, size_t size); -int qemu_mprotect_rwx(void *addr, size_t size); -int qemu_mprotect_none(void *addr, size_t size); - /* * Don't introduce new usage of this function, prefer the following * qemu_open/qemu_create that take an "Error **errp" diff --git a/tcg/region.c b/tcg/region.c index c46021d160..7b4e65a52e 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/madvise.h" +#include "qemu/mprotect.h" #include "qapi/error.h" #include "exec/exec-all.h" #include "tcg/tcg.h" diff --git a/util/osdep.c b/util/osdep.c index 8c5cd6e431..5181f86b82 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -39,6 +39,7 @@ extern int madvise(char *, size_t, int); #include "qemu/sockets.h" #include "qemu/error-report.h" #include "qemu/madvise.h" +#include "qemu/mprotect.h" #include "monitor/monitor.h" static bool fips_enabled = false; From 5b3e34315a8b2d985299735d685c71d481815bef Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 20:08:54 +0000 Subject: [PATCH 17/25] include: Move QEMU_MAP_* constants to mmap-alloc.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The QEMU_MAP_* constants are used only as arguments to the qemu_ram_mmap() function. Move them to mmap-alloc.h, where that function's prototype is defined. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20220208200856.3558249-4-peter.maydell@linaro.org --- include/qemu/mmap-alloc.h | 23 +++++++++++++++++++++++ include/qemu/osdep.h | 25 ------------------------- 2 files changed, 23 insertions(+), 25 deletions(-) diff --git a/include/qemu/mmap-alloc.h b/include/qemu/mmap-alloc.h index 90d0eee705..5076695cc8 100644 --- a/include/qemu/mmap-alloc.h +++ b/include/qemu/mmap-alloc.h @@ -35,4 +35,27 @@ void *qemu_ram_mmap(int fd, void qemu_ram_munmap(int fd, void *ptr, size_t size); +/* + * Abstraction of PROT_ and MAP_ flags as passed to mmap(), for example, + * consumed by qemu_ram_mmap(). + */ + +/* Map PROT_READ instead of PROT_READ | PROT_WRITE. */ +#define QEMU_MAP_READONLY (1 << 0) + +/* Use MAP_SHARED instead of MAP_PRIVATE. */ +#define QEMU_MAP_SHARED (1 << 1) + +/* + * Use MAP_SYNC | MAP_SHARED_VALIDATE if supported. Ignored without + * QEMU_MAP_SHARED. If mapping fails, warn and fallback to !QEMU_MAP_SYNC. + */ +#define QEMU_MAP_SYNC (1 << 2) + +/* + * Use MAP_NORESERVE to skip reservation of swap space (or huge pages if + * applicable). Bail out if not supported/effective. + */ +#define QEMU_MAP_NORESERVE (1 << 3) + #endif diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index ca00899bbd..165448b12f 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -401,31 +401,6 @@ static inline void qemu_cleanup_generic_vfree(void *p) */ #define QEMU_AUTO_VFREE __attribute__((cleanup(qemu_cleanup_generic_vfree))) -/* - * Abstraction of PROT_ and MAP_ flags as passed to mmap(), for example, - * consumed by qemu_ram_mmap(). - */ - -/* Map PROT_READ instead of PROT_READ | PROT_WRITE. */ -#define QEMU_MAP_READONLY (1 << 0) - -/* Use MAP_SHARED instead of MAP_PRIVATE. */ -#define QEMU_MAP_SHARED (1 << 1) - -/* - * Use MAP_SYNC | MAP_SHARED_VALIDATE if supported. Ignored without - * QEMU_MAP_SHARED. If mapping fails, warn and fallback to !QEMU_MAP_SYNC. - */ -#define QEMU_MAP_SYNC (1 << 2) - -/* - * Use MAP_NORESERVE to skip reservation of swap space (or huge pages if - * applicable). Bail out if not supported/effective. - */ -#define QEMU_MAP_NORESERVE (1 << 3) - - - #ifdef _WIN32 #define HAVE_CHARDEV_SERIAL 1 #elif defined(__linux__) || defined(__sun__) || defined(__FreeBSD__) \ From ad768e6f2a3397ec88ae874ad743df5d7c8c1936 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 20:08:55 +0000 Subject: [PATCH 18/25] include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The qemu_icache_linesize, qemu_icache_linesize_log, qemu_dcache_linesize, and qemu_dcache_linesize_log variables are not used in many files. Move them out of osdep.h to a new qemu/cacheinfo.h, and document them. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20220208200856.3558249-5-peter.maydell@linaro.org --- accel/tcg/translate-all.c | 1 + include/qemu/cacheinfo.h | 21 +++++++++++++++++++++ include/qemu/osdep.h | 5 ----- plugins/loader.c | 1 + tcg/region.c | 1 + tcg/tcg.c | 1 + util/atomic64.c | 1 + util/cacheflush.c | 1 + util/cacheinfo.c | 1 + 9 files changed, 28 insertions(+), 5 deletions(-) create mode 100644 include/qemu/cacheinfo.h diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bd71db59a9..5971cd53ab 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -51,6 +51,7 @@ #include "qemu/qemu-print.h" #include "qemu/timer.h" #include "qemu/main-loop.h" +#include "qemu/cacheinfo.h" #include "exec/log.h" #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" diff --git a/include/qemu/cacheinfo.h b/include/qemu/cacheinfo.h new file mode 100644 index 0000000000..019a157ea0 --- /dev/null +++ b/include/qemu/cacheinfo.h @@ -0,0 +1,21 @@ +/* + * QEMU host cacheinfo information + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef QEMU_CACHEINFO_H +#define QEMU_CACHEINFO_H + +/* + * These variables represent our best guess at the host icache and + * dcache sizes, expressed both as the size in bytes and as the + * base-2 log of the size in bytes. They are initialized at startup + * (via an attribute 'constructor' function). + */ +extern int qemu_icache_linesize; +extern int qemu_icache_linesize_log; +extern int qemu_dcache_linesize; +extern int qemu_dcache_linesize_log; + +#endif diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 165448b12f..61808edc69 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -616,11 +616,6 @@ pid_t qemu_fork(Error **errp); extern uintptr_t qemu_real_host_page_size; extern intptr_t qemu_real_host_page_mask; -extern int qemu_icache_linesize; -extern int qemu_icache_linesize_log; -extern int qemu_dcache_linesize; -extern int qemu_dcache_linesize_log; - /* * After using getopt or getopt_long, if you need to parse another set * of options, then you must reset optind. Unfortunately the way to diff --git a/plugins/loader.c b/plugins/loader.c index a4ec281692..4883b0a1cb 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -24,6 +24,7 @@ #include "qemu/rcu_queue.h" #include "qemu/qht.h" #include "qemu/bitmap.h" +#include "qemu/cacheinfo.h" #include "qemu/xxhash.h" #include "qemu/plugin.h" #include "hw/core/cpu.h" diff --git a/tcg/region.c b/tcg/region.c index 7b4e65a52e..72afb35738 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -26,6 +26,7 @@ #include "qemu/units.h" #include "qemu/madvise.h" #include "qemu/mprotect.h" +#include "qemu/cacheinfo.h" #include "qapi/error.h" #include "exec/exec-all.h" #include "tcg/tcg.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 5d2f0d8b10..528277d1d3 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -36,6 +36,7 @@ #include "qemu/qemu-print.h" #include "qemu/timer.h" #include "qemu/cacheflush.h" +#include "qemu/cacheinfo.h" /* Note: the long term plan is to reduce the dependencies on the QEMU CPU definitions. Currently they are used for qemu_ld/st diff --git a/util/atomic64.c b/util/atomic64.c index 93037d5b11..22983a970f 100644 --- a/util/atomic64.c +++ b/util/atomic64.c @@ -7,6 +7,7 @@ #include "qemu/osdep.h" #include "qemu/atomic.h" #include "qemu/thread.h" +#include "qemu/cacheinfo.h" #ifdef CONFIG_ATOMIC64 #error This file must only be compiled if !CONFIG_ATOMIC64 diff --git a/util/cacheflush.c b/util/cacheflush.c index 933355b0c9..4b57186d89 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -7,6 +7,7 @@ #include "qemu/osdep.h" #include "qemu/cacheflush.h" +#include "qemu/cacheinfo.h" #include "qemu/bitops.h" diff --git a/util/cacheinfo.c b/util/cacheinfo.c index b182f0b693..ab1644d490 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/atomic.h" +#include "qemu/cacheinfo.h" int qemu_icache_linesize = 0; int qemu_icache_linesize_log; From 15e09912b74c01bf8a8eebb4e61f4d0dbfe74513 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 8 Feb 2022 20:08:56 +0000 Subject: [PATCH 19/25] include: Move hardware version declarations to new qemu/hw-version.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The "hardware version" machinery (qemu_set_hw_version(), qemu_hw_version(), and the QEMU_HW_VERSION define) is used by fewer than 10 files. Move it out from osdep.h into a new qemu/hw-version.h. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20220208200856.3558249-6-peter.maydell@linaro.org --- hw/arm/nseries.c | 1 + hw/ide/core.c | 1 + hw/scsi/megasas.c | 1 + hw/scsi/scsi-bus.c | 1 + hw/scsi/scsi-disk.c | 1 + include/qemu/hw-version.h | 27 +++++++++++++++++++++++++++ include/qemu/osdep.h | 16 ---------------- softmmu/vl.c | 1 + target/i386/cpu.c | 1 + target/s390x/cpu_models.c | 1 + util/osdep.c | 1 + 11 files changed, 36 insertions(+), 16 deletions(-) create mode 100644 include/qemu/hw-version.h diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index af3164c551..9c1cafae86 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -24,6 +24,7 @@ #include "chardev/char.h" #include "qemu/cutils.h" #include "qemu/bswap.h" +#include "qemu/hw-version.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" diff --git a/hw/ide/core.c b/hw/ide/core.c index e28f8aad61..33463d9b8f 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -29,6 +29,7 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/timer.h" +#include "qemu/hw-version.h" #include "sysemu/sysemu.h" #include "sysemu/blockdev.h" #include "sysemu/dma.h" diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index cd43945827..d5dfb412ba 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -28,6 +28,7 @@ #include "hw/pci/msix.h" #include "qemu/iov.h" #include "qemu/module.h" +#include "qemu/hw-version.h" #include "hw/scsi/scsi.h" #include "scsi/constants.h" #include "trace.h" diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c index 4057e04ce8..b2e2bc3c96 100644 --- a/hw/scsi/scsi-bus.c +++ b/hw/scsi/scsi-bus.c @@ -3,6 +3,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/option.h" +#include "qemu/hw-version.h" #include "hw/qdev-properties.h" #include "hw/scsi/scsi.h" #include "migration/qemu-file-types.h" diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c index 9c0dc7b946..3666b8d946 100644 --- a/hw/scsi/scsi-disk.c +++ b/hw/scsi/scsi-disk.c @@ -25,6 +25,7 @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/module.h" +#include "qemu/hw-version.h" #include "hw/scsi/scsi.h" #include "migration/qemu-file-types.h" #include "migration/vmstate.h" diff --git a/include/qemu/hw-version.h b/include/qemu/hw-version.h new file mode 100644 index 0000000000..730a8c904d --- /dev/null +++ b/include/qemu/hw-version.h @@ -0,0 +1,27 @@ +/* + * QEMU "hardware version" machinery + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef QEMU_HW_VERSION_H +#define QEMU_HW_VERSION_H + +/* + * Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default + * instead of QEMU_VERSION, so setting hw_version on MachineClass + * is no longer mandatory. + * + * Do NOT change this string, or it will break compatibility on all + * machine classes that don't set hw_version. + */ +#define QEMU_HW_VERSION "2.5+" + +/* QEMU "hardware version" setting. Used to replace code that exposed + * QEMU_VERSION to guests in the past and need to keep compatibility. + * Do not use qemu_hw_version() in new code. + */ +void qemu_set_hw_version(const char *); +const char *qemu_hw_version(void); + +#endif diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 61808edc69..7bcce3bceb 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -534,22 +534,6 @@ static inline void qemu_timersub(const struct timeval *val1, void qemu_set_cloexec(int fd); -/* Starting on QEMU 2.5, qemu_hw_version() returns "2.5+" by default - * instead of QEMU_VERSION, so setting hw_version on MachineClass - * is no longer mandatory. - * - * Do NOT change this string, or it will break compatibility on all - * machine classes that don't set hw_version. - */ -#define QEMU_HW_VERSION "2.5+" - -/* QEMU "hardware version" setting. Used to replace code that exposed - * QEMU_VERSION to guests in the past and need to keep compatibility. - * Do not use qemu_hw_version() in new code. - */ -void qemu_set_hw_version(const char *); -const char *qemu_hw_version(void); - void fips_set_state(bool requested); bool fips_get_state(void); diff --git a/softmmu/vl.c b/softmmu/vl.c index 5e1b35ba48..1fe028800f 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -36,6 +36,7 @@ #include "qemu-version.h" #include "qemu/cutils.h" #include "qemu/help_option.h" +#include "qemu/hw-version.h" #include "qemu/uuid.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" diff --git a/target/i386/cpu.c b/target/i386/cpu.c index aa9e636800..c9954df4a7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -21,6 +21,7 @@ #include "qemu/units.h" #include "qemu/cutils.h" #include "qemu/qemu-print.h" +#include "qemu/hw-version.h" #include "cpu.h" #include "tcg/helper-tcg.h" #include "sysemu/reset.h" diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 11e06cc51f..17ae771939 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -19,6 +19,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "qemu/module.h" +#include "qemu/hw-version.h" #include "qemu/qemu-print.h" #ifndef CONFIG_USER_ONLY #include "sysemu/sysemu.h" diff --git a/util/osdep.c b/util/osdep.c index 5181f86b82..723cdcb004 100644 --- a/util/osdep.c +++ b/util/osdep.c @@ -40,6 +40,7 @@ extern int madvise(char *, size_t, int); #include "qemu/error-report.h" #include "qemu/madvise.h" #include "qemu/mprotect.h" +#include "qemu/hw-version.h" #include "monitor/monitor.h" static bool fips_enabled = false; From af643498d2541113e64602624b788a2d7deab084 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Sun, 13 Feb 2022 11:12:15 +0900 Subject: [PATCH 20/25] MAINTAINERS: Add Akihiko Odaki to macOS-relateds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Akihiko Odaki Reviewed-by: Christian Schoenebeck Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220213021215.1974-1-akihiko.odaki@gmail.com Signed-off-by: Peter Maydell --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bd85e27889..c3b500345c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2416,6 +2416,7 @@ F: audio/alsaaudio.c Core Audio framework backend M: Gerd Hoffmann R: Christian Schoenebeck +R: Akihiko Odaki S: Odd Fixes F: audio/coreaudio.c @@ -2668,6 +2669,7 @@ F: util/drm.c Cocoa graphics M: Peter Maydell +R: Akihiko Odaki S: Odd Fixes F: ui/cocoa.m From 432732b5e455ef0b28304004a3ca2b96ae33e39d Mon Sep 17 00:00:00 2001 From: Pavel Dovgalyuk Date: Mon, 7 Feb 2022 11:44:19 +0300 Subject: [PATCH 21/25] hw/timer: fix a9gtimer vmstate A9 gtimer includes global control field and number of per-cpu fields. But only per-cpu ones are migrated. This patch adds a subsection for global control field migration. Signed-off-by: Pavel Dovgalyuk Message-id: 164422345976.2186660.1104517592452494510.stgit@pasha-ThinkPad-X280 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/timer/a9gtimer.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 7233068a37..5e959b6d09 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -318,6 +318,12 @@ static void a9_gtimer_realize(DeviceState *dev, Error **errp) } } +static bool vmstate_a9_gtimer_control_needed(void *opaque) +{ + A9GTimerState *s = opaque; + return s->control != 0; +} + static const VMStateDescription vmstate_a9_gtimer_per_cpu = { .name = "arm.cortex-a9-global-timer.percpu", .version_id = 1, @@ -331,6 +337,17 @@ static const VMStateDescription vmstate_a9_gtimer_per_cpu = { } }; +static const VMStateDescription vmstate_a9_gtimer_control = { + .name = "arm.cortex-a9-global-timer.control", + .version_id = 1, + .minimum_version_id = 1, + .needed = vmstate_a9_gtimer_control_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT32(control, A9GTimerState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_a9_gtimer = { .name = "arm.cortex-a9-global-timer", .version_id = 1, @@ -344,6 +361,10 @@ static const VMStateDescription vmstate_a9_gtimer = { 1, vmstate_a9_gtimer_per_cpu, A9GTimerPerCPU), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription*[]) { + &vmstate_a9_gtimer_control, + NULL } }; From ca6d63c20ba25e8e931157fbe7f144fb397c0f72 Mon Sep 17 00:00:00 2001 From: Patrick Venture Date: Tue, 8 Feb 2022 15:31:04 -0800 Subject: [PATCH 22/25] hw/arm: add initial mori-bmc board This is the BMC attached to the OpenBMC Mori board. Signed-off-by: Patrick Venture Reviewed-by: Chris Rauer Reviewed-by: Ilkyun Choi Message-id: 20220208233104.284425-1-venture@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/nuvoton.rst | 1 + hw/arm/npcm7xx_boards.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index adf497e679..ef2792076a 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -21,6 +21,7 @@ Hyperscale applications. The following machines are based on this chip : - ``quanta-gbs-bmc`` Quanta GBS server BMC - ``quanta-gsj`` Quanta GSJ server BMC - ``kudo-bmc`` Fii USA Kudo server BMC +- ``mori-bmc`` Fii USA Mori server BMC There are also two more SoCs, NPCM710 and NPCM705, which are single-core variants of NPCM750 and NPCM730, respectively. These are currently not diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index d701e5cc55..0678a56156 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -34,6 +34,7 @@ #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff #define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff #define KUDO_BMC_POWER_ON_STRAPS 0x00001fff +#define MORI_BMC_POWER_ON_STRAPS 0x00001fff static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin"; @@ -429,6 +430,21 @@ static void kudo_bmc_init(MachineState *machine) npcm7xx_load_kernel(machine, soc); } +static void mori_bmc_init(MachineState *machine) +{ + NPCM7xxState *soc; + + soc = npcm7xx_create_soc(machine, MORI_BMC_POWER_ON_STRAPS); + npcm7xx_connect_dram(soc, machine->ram); + qdev_realize(DEVICE(soc), NULL, &error_fatal); + + npcm7xx_load_bootrom(machine, soc); + npcm7xx_connect_flash(&soc->fiu[1], 0, "mx66u51235f", + drive_get(IF_MTD, 3, 0)); + + npcm7xx_load_kernel(machine, soc); +} + static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type) { NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type)); @@ -501,6 +517,18 @@ static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; }; +static void mori_bmc_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc = MACHINE_CLASS(oc); + + npcm7xx_set_soc_type(nmc, TYPE_NPCM730); + + mc->desc = "Mori BMC (Cortex-A9)"; + mc->init = mori_bmc_init; + mc->default_ram_size = 1 * GiB; +} + static const TypeInfo npcm7xx_machine_types[] = { { .name = TYPE_NPCM7XX_MACHINE, @@ -525,6 +553,10 @@ static const TypeInfo npcm7xx_machine_types[] = { .name = MACHINE_TYPE_NAME("kudo-bmc"), .parent = TYPE_NPCM7XX_MACHINE, .class_init = kudo_bmc_machine_class_init, + }, { + .name = MACHINE_TYPE_NAME("mori-bmc"), + .parent = TYPE_NPCM7XX_MACHINE, + .class_init = mori_bmc_machine_class_init, }, }; From 0cd723f2d0afc48bb44c40d8aa1bce68848667ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 15 Feb 2022 09:03:02 +0100 Subject: [PATCH 23/25] ui/cocoa: Remove allowedFileTypes restriction in SavePanel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit setAllowedFileTypes is deprecated in macOS 12. Per Akihiko Odaki [*]: An image file, which is being chosen by the panel, can be a raw file and have a variety of file extensions and many are not covered by the provided list (e.g. "udf"). Other platforms like GTK can provide an option to open a file with an extension not listed, but Cocoa can't. It forces the user to rename the file to give an extension in the list. Moreover, Cocoa does not tell which extensions are in the list so the user needs to read the source code, which is pretty bad. Since this code is harming the usability rather than improving it, simply remove the [NSSavePanel allowedFileTypes:] call, fixing: [2789/6622] Compiling Objective-C object libcommon.fa.p/ui_cocoa.m.o ui/cocoa.m:1411:16: error: 'setAllowedFileTypes:' is deprecated: first deprecated in macOS 12.0 - Use -allowedContentTypes instead [-Werror,-Wdeprecated-declarations] [openPanel setAllowedFileTypes: supportedImageFileTypes]; ^ /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSSavePanel.h:215:49: note: property 'allowedFileTypes' is declared deprecated here @property (nullable, copy) NSArray *allowedFileTypes API_DEPRECATED("Use -allowedContentTypes instead", macos(10.3,12.0)); ^ /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSSavePanel.h:215:49: note: 'setAllowedFileTypes:' has been explicitly marked deprecated here FAILED: libcommon.fa.p/ui_cocoa.m.o [*] https://lore.kernel.org/qemu-devel/4dde2e66-63cb-4390-9538-c032310db3e3@gmail.com/ Suggested-by: Akihiko Odaki Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Christian Schoenebeck Signed-off-by: Philippe Mathieu-Daudé Message-id: 20220215080307.69550-11-f4bug@amsat.org Reviewed by: Cameron Esfahani Reviewed-by: Akihiko Odaki Tested-by: Akihiko Odaki Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- ui/cocoa.m | 6 ------ 1 file changed, 6 deletions(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index ac18e14ce0..7a1ddd4075 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -100,7 +100,6 @@ static int gArgc; static char **gArgv; static bool stretch_video; static NSTextField *pauseLabel; -static NSArray * supportedImageFileTypes; static QemuSemaphore display_init_sem; static QemuSemaphore app_started_sem; @@ -1168,10 +1167,6 @@ QemuCocoaView *cocoaView; [pauseLabel setTextColor: [NSColor blackColor]]; [pauseLabel sizeToFit]; - // set the supported image file types that can be opened - supportedImageFileTypes = [NSArray arrayWithObjects: @"img", @"iso", @"dmg", - @"qcow", @"qcow2", @"cloop", @"vmdk", @"cdr", - @"toast", nil]; [self make_about_window]; } return self; @@ -1414,7 +1409,6 @@ QemuCocoaView *cocoaView; openPanel = [NSOpenPanel openPanel]; [openPanel setCanChooseFiles: YES]; [openPanel setAllowsMultipleSelection: NO]; - [openPanel setAllowedFileTypes: supportedImageFileTypes]; if([openPanel runModal] == NSModalResponseOK) { NSString * file = [[[openPanel URLs] objectAtIndex: 0] path]; if(file == nil) { From b597278d5780b15759c31a944f21f8b1491902fe Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Tue, 15 Feb 2022 09:03:04 +0100 Subject: [PATCH 24/25] ui/cocoa: Do not alert even without block devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Akihiko Odaki Message-id: 20220215080307.69550-13-f4bug@amsat.org Message-Id: <20220213021418.2155-1-akihiko.odaki@gmail.com> Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- ui/cocoa.m | 5 ----- 1 file changed, 5 deletions(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index 7a1ddd4075..f585a5c177 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -1709,11 +1709,6 @@ static void addRemovableDevicesMenuItems(void) currentDevice = qmp_query_block(NULL); pointerToFree = currentDevice; - if(currentDevice == NULL) { - NSBeep(); - QEMU_Alert(@"Failed to query for block devices!"); - return; - } menu = [[[NSApp mainMenu] itemWithTitle:@"Machine"] submenu]; From ca511604925eef8572e22ecbf0d3c758d7277924 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Tue, 15 Feb 2022 09:03:05 +0100 Subject: [PATCH 25/25] ui/cocoa: Fix the leak of qemu_console_get_label MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Message-id: 20220215080307.69550-14-f4bug@amsat.org Message-Id: <20220213021329.2066-1-akihiko.odaki@gmail.com> [PMD: Use g_autofree, suggested by Zoltan BALATON] Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- ui/cocoa.m | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index f585a5c177..a8f1cdaf92 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -1674,7 +1674,9 @@ static void create_initial_menus(void) /* Returns a name for a given console */ static NSString * getConsoleName(QemuConsole * console) { - return [NSString stringWithFormat: @"%s", qemu_console_get_label(console)]; + g_autofree char *label = qemu_console_get_label(console); + + return [NSString stringWithUTF8String:label]; } /* Add an entry to the View menu for each console */