mirror of https://github.com/xemu-project/xemu.git
target/mips/translate: Add declarations for generic code
Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
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@ -38,11 +38,6 @@
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#include "fpu_helper.h"
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#include "translate.h"
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#define MIPS_DEBUG_DISAS 0
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/* MIPS major opcodes */
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#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
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enum {
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/* indirect opcode tables */
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OPC_SPECIAL = (0x00 << 26),
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@ -2491,9 +2486,10 @@ enum {
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};
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/* global register indices */
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static TCGv cpu_gpr[32], cpu_PC;
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TCGv cpu_gpr[32], cpu_PC;
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static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
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static TCGv cpu_dspctrl, btarget, bcond;
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static TCGv cpu_dspctrl, btarget;
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TCGv bcond;
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static TCGv cpu_lladdr, cpu_llval;
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static TCGv_i32 hflags;
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static TCGv_i32 fpu_fcr0, fpu_fcr31;
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@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] = {
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};
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#endif
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#define LOG_DISAS(...) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
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} \
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} while (0)
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#define MIPS_INVAL(op) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, \
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TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
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ctx->base.pc_next, ctx->opcode, op, \
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ctx->opcode >> 26, ctx->opcode & 0x3F, \
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((ctx->opcode >> 16) & 0x1F)); \
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} \
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} while (0)
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/* General purpose registers moves. */
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static inline void gen_load_gpr(TCGv t, int reg)
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void gen_load_gpr(TCGv t, int reg)
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{
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if (reg == 0) {
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tcg_gen_movi_tl(t, 0);
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@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg)
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}
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}
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static inline void gen_store_gpr(TCGv t, int reg)
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void gen_store_gpr(TCGv t, int reg)
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{
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if (reg != 0) {
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tcg_gen_mov_tl(cpu_gpr[reg], t);
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@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
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void generate_exception_err(DisasContext *ctx, int excp, int err)
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{
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TCGv_i32 texcp = tcg_const_i32(excp);
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TCGv_i32 terr = tcg_const_i32(err);
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@ -2774,12 +2752,12 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static inline void generate_exception(DisasContext *ctx, int excp)
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void generate_exception(DisasContext *ctx, int excp)
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{
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gen_helper_0e0i(raise_exception, excp);
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}
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static inline void generate_exception_end(DisasContext *ctx, int excp)
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void generate_exception_end(DisasContext *ctx, int excp)
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{
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generate_exception_err(ctx, excp, 0);
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}
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@ -2859,8 +2837,7 @@ static inline int get_fp_bit(int cc)
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}
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/* Addresses computation */
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static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0,
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TCGv arg1)
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void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
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{
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tcg_gen_add_tl(ret, arg0, arg1);
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@ -2898,7 +2875,7 @@ static target_long addr_add(DisasContext *ctx, target_long base,
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}
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/* Sign-extract the low 32-bits to a target_long. */
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static inline void gen_move_low32(TCGv ret, TCGv_i64 arg)
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void gen_move_low32(TCGv ret, TCGv_i64 arg)
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{
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#if defined(TARGET_MIPS64)
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tcg_gen_ext32s_i64(ret, arg);
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@ -2908,7 +2885,7 @@ static inline void gen_move_low32(TCGv ret, TCGv_i64 arg)
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}
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/* Sign-extract the high 32-bits to a target_long. */
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static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
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void gen_move_high32(TCGv ret, TCGv_i64 arg)
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{
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#if defined(TARGET_MIPS64)
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tcg_gen_sari_i64(ret, arg, 32);
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@ -3013,7 +2990,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
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* This code generates a "reserved instruction" exception if the
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* CPU does not support the instruction set corresponding to flags.
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*/
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static inline void check_insn(DisasContext *ctx, uint64_t flags)
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void check_insn(DisasContext *ctx, uint64_t flags)
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{
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if (unlikely(!(ctx->insn_flags & flags))) {
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generate_exception_end(ctx, EXCP_RI);
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@ -3064,7 +3041,7 @@ static inline void check_ps(DisasContext *ctx)
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* This code generates a "reserved instruction" exception if 64-bit
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* instructions are not enabled.
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*/
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static inline void check_mips_64(DisasContext *ctx)
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void check_mips_64(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
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generate_exception_end(ctx, EXCP_RI);
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@ -3390,8 +3367,7 @@ OP_LD_ATOMIC(lld, ld64);
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#endif
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#undef OP_LD_ATOMIC
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static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
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int base, int offset)
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void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
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{
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if (base == 0) {
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tcg_gen_movi_tl(addr, offset);
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@ -10,6 +10,8 @@
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#include "exec/translator.h"
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#define MIPS_DEBUG_DISAS 0
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typedef struct DisasContext {
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DisasContextBase base;
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target_ulong saved_pc;
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@ -47,4 +49,45 @@ typedef struct DisasContext {
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int gi;
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} DisasContext;
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/* MIPS major opcodes */
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#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
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void generate_exception(DisasContext *ctx, int excp);
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void generate_exception_err(DisasContext *ctx, int excp, int err);
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void generate_exception_end(DisasContext *ctx, int excp);
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void check_insn(DisasContext *ctx, uint64_t flags);
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#ifdef TARGET_MIPS64
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void check_mips_64(DisasContext *ctx);
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#endif
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void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
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void gen_move_low32(TCGv ret, TCGv_i64 arg);
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void gen_move_high32(TCGv ret, TCGv_i64 arg);
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void gen_load_gpr(TCGv t, int reg);
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void gen_store_gpr(TCGv t, int reg);
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void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
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extern TCGv cpu_gpr[32], cpu_PC;
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extern TCGv bcond;
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#define LOG_DISAS(...) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
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} \
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} while (0)
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#define MIPS_INVAL(op) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, \
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TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
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ctx->base.pc_next, ctx->opcode, op, \
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ctx->opcode >> 26, ctx->opcode & 0x3F, \
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((ctx->opcode >> 16) & 0x1F)); \
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} \
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} while (0)
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#endif
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