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Misc hardware patch queue 

- MAINTAINERS updates (Zoltan, Thomas)
 - Fix cutils::get_relocated_path on Windows host (Akihiko)
 - Housekeeping in Memory APIs (Marc-André)
 - SDHCI fix for SDMA transfer (Lu, Jianxian)
 - Various QOM/QDev/SysBus cleanups (Philippe)
 - Constify QemuInputHandler structure (Philippe)
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Merge tag 'hw-misc-20231019' of https://github.com/philmd/qemu into staging

Misc hardware patch queue

- MAINTAINERS updates (Zoltan, Thomas)
- Fix cutils::get_relocated_path on Windows host (Akihiko)
- Housekeeping in Memory APIs (Marc-André)
- SDHCI fix for SDMA transfer (Lu, Jianxian)
- Various QOM/QDev/SysBus cleanups (Philippe)
- Constify QemuInputHandler structure (Philippe)

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# gpg: Signature made Thu 19 Oct 2023 14:16:16 PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20231019' of https://github.com/philmd/qemu: (46 commits)
  ui/input: Constify QemuInputHandler structure
  hw/net: Declare link using static DEFINE_PROP_LINK() macro
  hw/dma: Declare link using static DEFINE_PROP_LINK() macro
  hw/scsi/virtio-scsi: Use VIRTIO_SCSI_COMMON() macro
  hw/display/virtio-gpu: Use VIRTIO_DEVICE() macro
  hw/block/vhost-user-blk: Use DEVICE() / VIRTIO_DEVICE() macros
  hw/virtio/virtio-pmem: Replace impossible check by assertion
  hw/s390x/css-bridge: Realize sysbus device before accessing it
  hw/isa: Realize ISA bridge device before accessing it
  hw/arm/virt: Realize ARM_GICV2M sysbus device before accessing it
  hw/acpi: Realize ACPI_GED sysbus device before accessing it
  hw/pci-host/bonito: Do not use SysBus API to map local MMIO region
  hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region
  hw/misc/allwinner-dramc: Move sysbus_mmio_map call from init -> realize
  hw/i386/intel_iommu: Do not use SysBus API to map local MMIO region
  hw/i386/amd_iommu: Do not use SysBus API to map local MMIO region
  hw/audio/pcspk: Inline pcspk_init()
  hw/intc/spapr_xive: Do not use SysBus API to map local MMIO region
  hw/intc/spapr_xive: Move sysbus_init_mmio() calls around
  hw/ppc/pnv: Do not use SysBus API to map local MMIO region
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-10-20 06:46:03 -07:00
parent 31572e63cd b1be65f643
commit 46919512fc
72 changed files with 232 additions and 273 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.mailmap
View File

@ -81,6 +81,9 @@ Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
Paul Brook <paul@nowt.org> <paul@codesourcery.com>
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>

16
MAINTAINERS
View File

@ -295,6 +295,7 @@ S: Odd Fixes
F: docs/system/openrisc/cpu-features.rst
F: target/openrisc/
F: hw/openrisc/
F: include/hw/openrisc/
F: tests/tcg/openrisc/
PowerPC TCG CPUs
@ -1179,9 +1180,11 @@ R: Helge Deller <deller@gmx.de>
S: Odd Fixes
F: configs/devices/hppa-softmmu/default.mak
F: hw/hppa/
F: hw/input/lasips2.c
F: hw/net/*i82596*
F: hw/misc/lasi.c
F: hw/pci-host/dino.c
F: include/hw/input/lasips2.h
F: include/hw/misc/lasi.h
F: include/hw/net/lasi_82596.h
F: include/hw/pci-host/dino.h
@ -1322,10 +1325,7 @@ M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Odd Fixes
F: hw/mips/fuloong2e.c
F: hw/isa/vt82c686.c
F: hw/pci-host/bonito.c
F: hw/usb/vt82c686-uhci-pci.c
F: include/hw/isa/vt82c686.h
F: include/hw/pci-host/bonito.h
F: tests/avocado/machine_mips_fuloong2e.py
@ -1337,6 +1337,7 @@ F: hw/intc/loongson_liointc.c
F: hw/mips/loongson3_bootp.c
F: hw/mips/loongson3_bootp.h
F: hw/mips/loongson3_virt.c
F: include/hw/intc/loongson_liointc.h
F: tests/avocado/machine_mips_loongson3v.py
Boston
@ -2481,6 +2482,15 @@ S: Maintained
F: hw/isa/piix4.c
F: include/hw/southbridge/piix.h
VIA South Bridges (VT82C686B, VT8231)
M: BALATON Zoltan <balaton@eik.bme.hu>
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Maintained
F: hw/isa/vt82c686.c
F: hw/usb/vt82c686-uhci-pci.c
F: include/hw/isa/vt82c686.h
Firmware configuration (fw_cfg)
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Gerd Hoffmann <kraxel@redhat.com>

2
chardev/msmouse.c
View File

@ -171,7 +171,7 @@ static int msmouse_chr_write(struct Chardev *s, const uint8_t *buf, int len)
return len;
}
static QemuInputHandler msmouse_handler = {
static const QemuInputHandler msmouse_handler = {
.name = "QEMU Microsoft Mouse",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_REL,
.event = msmouse_input_event,

2
chardev/wctablet.c
View File

@ -178,7 +178,7 @@ static void wctablet_input_sync(DeviceState *dev)
}
}
static QemuInputHandler wctablet_handler = {
static const QemuInputHandler wctablet_handler = {
.name = "QEMU Wacom Pen Tablet",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_ABS,
.event = wctablet_input_event,

5
hw/acpi/pcihp.c
View File

@ -496,8 +496,7 @@ static const MemoryRegionOps acpi_pcihp_io_ops = {
};
void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
MemoryRegion *address_space_io,
uint16_t io_base)
MemoryRegion *io, uint16_t io_base)
{
s->io_len = ACPI_PCIHP_SIZE;
s->io_base = io_base;
@ -506,7 +505,7 @@ void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
"acpi-pci-hotplug", s->io_len);
memory_region_add_subregion(address_space_io, s->io_base, &s->io);
memory_region_add_subregion(io, s->io_base, &s->io);
object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
OBJ_PROP_FLAG_READ);

5
hw/arm/virt.c
View File

@ -651,13 +651,12 @@ static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}
@ -695,10 +694,10 @@ static void create_v2m(VirtMachineState *vms)
DeviceState *dev;
dev = qdev_new("arm-gicv2m");
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
qdev_prop_set_uint32(dev, "base-spi", irq);
qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
for (i = 0; i < NUM_GICV2M_SPIS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,

4
hw/block/vhost-user-blk.c
View File

@ -405,7 +405,7 @@ static void vhost_user_blk_event(void *opaque, QEMUChrEvent event)
static int vhost_user_blk_realize_connect(VHostUserBlk *s, Error **errp)
{
DeviceState *dev = &s->parent_obj.parent_obj;
DeviceState *dev = DEVICE(s);
int ret;
s->connected = false;
@ -423,7 +423,7 @@ static int vhost_user_blk_realize_connect(VHostUserBlk *s, Error **errp)
assert(s->connected);
ret = vhost_dev_get_config(&s->dev, (uint8_t *)&s->blkcfg,
s->parent_obj.config_len, errp);
VIRTIO_DEVICE(s)->config_len, errp);
if (ret < 0) {
qemu_chr_fe_disconnect(&s->chardev);
vhost_dev_cleanup(&s->dev);

2
hw/char/escc.c
View File

@ -845,7 +845,7 @@ static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src,
put_queue(s, keycode);
}
static QemuInputHandler sunkbd_handler = {
static const QemuInputHandler sunkbd_handler = {
.name = "sun keyboard",
.mask = INPUT_EVENT_MASK_KEY,
.event = sunkbd_handle_event,

6
hw/core/cpu-sysemu.c
View File

@ -34,17 +34,17 @@ bool cpu_paging_enabled(const CPUState *cpu)
return false;
}
void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->sysemu_ops->get_memory_mapping) {
cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
return cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
}
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
return false;
}
hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,

2
hw/display/virtio-gpu.c
View File

@ -1128,7 +1128,7 @@ static void virtio_gpu_ctrl_bh(void *opaque)
VirtIOGPU *g = opaque;
VirtIOGPUClass *vgc = VIRTIO_GPU_GET_CLASS(g);
vgc->handle_ctrl(&g->parent_obj.parent_obj, g->ctrl_vq);
vgc->handle_ctrl(VIRTIO_DEVICE(g), g->ctrl_vq);
}
static void virtio_gpu_handle_cursor(VirtIODevice *vdev, VirtQueue *vq)

6
hw/display/xenfb.c
View File

@ -321,20 +321,20 @@ static void xenfb_mouse_sync(DeviceState *dev)
xenfb->wheel = 0;
}
static QemuInputHandler xenfb_keyboard = {
static const QemuInputHandler xenfb_keyboard = {
.name = "Xen PV Keyboard",
.mask = INPUT_EVENT_MASK_KEY,
.event = xenfb_key_event,
};
static QemuInputHandler xenfb_abs_mouse = {
static const QemuInputHandler xenfb_abs_mouse = {
.name = "Xen PV Mouse",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_ABS,
.event = xenfb_mouse_event,
.sync = xenfb_mouse_sync,
};
static QemuInputHandler xenfb_rel_mouse = {
static const QemuInputHandler xenfb_rel_mouse = {
.name = "Xen PV Mouse",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_REL,
.event = xenfb_mouse_event,

6
hw/dma/xilinx_axidma.c
View File

@ -577,10 +577,6 @@ static void xilinx_axidma_init(Object *obj)
object_initialize_child(OBJECT(s), "axistream-control-connected-target",
&s->rx_control_dev,
TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->dma_mr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
sysbus_init_irq(sbd, &s->streams[0].irq);
sysbus_init_irq(sbd, &s->streams[1].irq);
@ -596,6 +592,8 @@ static Property axidma_properties[] = {
tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_LINK("dma", XilinxAXIDMA, dma_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};

7
hw/dma/xlnx-zdma.c
View File

@ -795,11 +795,6 @@ static void zdma_init(Object *obj)
TYPE_XLNX_ZDMA, ZDMA_R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq_zdma_ch_imr);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->dma_mr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
static const VMStateDescription vmstate_zdma = {
@ -817,6 +812,8 @@ static const VMStateDescription vmstate_zdma = {
static Property zdma_props[] = {
DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64),
DEFINE_PROP_LINK("dma", XlnxZDMA, dma_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};

13
hw/dma/xlnx_csu_dma.c
View File

@ -702,6 +702,10 @@ static Property xlnx_csu_dma_properties[] = {
* which channel the device is connected to.
*/
DEFINE_PROP_BOOL("is-dst", XlnxCSUDMA, is_dst, true),
DEFINE_PROP_LINK("stream-connected-dma", XlnxCSUDMA, tx_dev,
TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_LINK("dma", XlnxCSUDMA, dma_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
@ -728,15 +732,6 @@ static void xlnx_csu_dma_init(Object *obj)
memory_region_init(&s->iomem, obj, TYPE_XLNX_CSU_DMA,
XLNX_CSU_DMA_R_MAX * 4);
object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK,
(Object **)&s->tx_dev,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->dma_mr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
static const TypeInfo xlnx_csu_dma_info = {

5
hw/i386/amd_iommu.c
View File

@ -1579,9 +1579,8 @@ static void amdvi_sysbus_realize(DeviceState *dev, Error **errp)
/* set up MMIO */
memory_region_init_io(&s->mmio, OBJECT(s), &mmio_mem_ops, s, "amdvi-mmio",
AMDVI_MMIO_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, AMDVI_BASE_ADDR);
memory_region_add_subregion(get_system_memory(), AMDVI_BASE_ADDR,
&s->mmio);
pci_setup_iommu(bus, amdvi_host_dma_iommu, s);
amdvi_init(s);
}

5
hw/i386/intel_iommu.c
View File

@ -4134,6 +4134,8 @@ static void vtd_realize(DeviceState *dev, Error **errp)
qemu_mutex_init(&s->iommu_lock);
memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
"intel_iommu", DMAR_REG_SIZE);
memory_region_add_subregion(get_system_memory(),
Q35_HOST_BRIDGE_IOMMU_ADDR, &s->csrmem);
/* Create the shared memory regions by all devices */
memory_region_init(&s->mr_nodmar, OBJECT(s), "vtd-nodmar",
@ -4148,15 +4150,12 @@ static void vtd_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion_overlap(&s->mr_nodmar,
VTD_INTERRUPT_ADDR_FIRST,
&s->mr_ir, 1);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
/* No corresponding destroy */
s->iotlb = g_hash_table_new_full(vtd_iotlb_hash, vtd_iotlb_equal,
g_free, g_free);
s->vtd_address_spaces = g_hash_table_new_full(vtd_as_hash, vtd_as_equal,
g_free, g_free);
vtd_init(s);
sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
/* Pseudo address space under root PCI bus. */
x86ms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);

2
hw/i386/microvm.c
View File

@ -206,12 +206,12 @@ static void microvm_devices_init(MicrovmMachineState *mms)
if (x86_machine_is_acpi_enabled(x86ms)) {
DeviceState *dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", ACPI_GED_PWR_DOWN_EVT);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, GED_MMIO_BASE);
/* sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, GED_MMIO_BASE_MEMHP); */
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, GED_MMIO_BASE_REGS);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
x86ms->gsi[GED_MMIO_IRQ]);
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
x86ms->acpi_dev = HOTPLUG_HANDLER(dev);
}

4
hw/i386/pc.c
View File

@ -1283,7 +1283,9 @@ void pc_basic_device_init(struct PCMachineState *pcms,
/* connect PIT to output control line of the HPET */
qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
}
pcspk_init(pcms->pcspk, isa_bus, pit);
object_property_set_link(OBJECT(pcms->pcspk), "pit",
OBJECT(pit), &error_fatal);
isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
}
/* Super I/O */

2
hw/input/adb-kbd.c
View File

@ -355,7 +355,7 @@ static void adb_kbd_reset(DeviceState *dev)
s->count = 0;
}
static QemuInputHandler adb_keyboard_handler = {
static const QemuInputHandler adb_keyboard_handler = {
.name = "QEMU ADB Keyboard",
.mask = INPUT_EVENT_MASK_KEY,
.event = adb_keyboard_event,

6
hw/input/hid.c
View File

@ -510,20 +510,20 @@ void hid_free(HIDState *hs)
hid_del_idle_timer(hs);
}
static QemuInputHandler hid_keyboard_handler = {
static const QemuInputHandler hid_keyboard_handler = {
.name = "QEMU HID Keyboard",
.mask = INPUT_EVENT_MASK_KEY,
.event = hid_keyboard_event,
};
static QemuInputHandler hid_mouse_handler = {
static const QemuInputHandler hid_mouse_handler = {
.name = "QEMU HID Mouse",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_REL,
.event = hid_pointer_event,
.sync = hid_pointer_sync,
};
static QemuInputHandler hid_tablet_handler = {
static const QemuInputHandler hid_tablet_handler = {
.name = "QEMU HID Tablet",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_ABS,
.event = hid_pointer_event,

4
hw/input/ps2.c
View File

@ -1231,7 +1231,7 @@ static const VMStateDescription vmstate_ps2_mouse = {
}
};
static QemuInputHandler ps2_keyboard_handler = {
static const QemuInputHandler ps2_keyboard_handler = {
.name = "QEMU PS/2 Keyboard",
.mask = INPUT_EVENT_MASK_KEY,
.event = ps2_keyboard_event,
@ -1242,7 +1242,7 @@ static void ps2_kbd_realize(DeviceState *dev, Error **errp)
qemu_input_handler_register(dev, &ps2_keyboard_handler);
}
static QemuInputHandler ps2_mouse_handler = {
static const QemuInputHandler ps2_mouse_handler = {
.name = "QEMU PS/2 Mouse",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_REL,
.event = ps2_mouse_event,

8
hw/input/virtio-input-hid.c
View File

@ -265,7 +265,7 @@ static const TypeInfo virtio_input_hid_info = {
/* ----------------------------------------------------------------- */
static QemuInputHandler virtio_keyboard_handler = {
static const QemuInputHandler virtio_keyboard_handler = {
.name = VIRTIO_ID_NAME_KEYBOARD,
.mask = INPUT_EVENT_MASK_KEY,
.event = virtio_input_handle_event,
@ -322,7 +322,7 @@ static const TypeInfo virtio_keyboard_info = {
/* ----------------------------------------------------------------- */
static QemuInputHandler virtio_mouse_handler = {
static const QemuInputHandler virtio_mouse_handler = {
.name = VIRTIO_ID_NAME_MOUSE,
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_REL,
.event = virtio_input_handle_event,
@ -416,7 +416,7 @@ static const TypeInfo virtio_mouse_info = {
/* ----------------------------------------------------------------- */
static QemuInputHandler virtio_tablet_handler = {
static const QemuInputHandler virtio_tablet_handler = {
.name = VIRTIO_ID_NAME_TABLET,
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_ABS,
.event = virtio_input_handle_event,
@ -541,7 +541,7 @@ static const TypeInfo virtio_tablet_info = {
/* ----------------------------------------------------------------- */
static QemuInputHandler virtio_multitouch_handler = {
static const QemuInputHandler virtio_multitouch_handler = {
.name = VIRTIO_ID_NAME_MULTITOUCH,
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_MTT,
.event = virtio_input_handle_event,

4
hw/intc/apic_common.c
View File

@ -257,6 +257,7 @@ static const VMStateDescription vmstate_apic_common;
static void apic_common_realize(DeviceState *dev, Error **errp)
{
ERRP_GUARD();
APICCommonState *s = APIC_COMMON(dev);
APICCommonClass *info;
static DeviceState *vapic;
@ -267,6 +268,9 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
info = APIC_COMMON_GET_CLASS(s);
info->realize(dev, errp);
if (*errp) {
return;
}
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&

12
hw/intc/spapr_xive.c
View File

@ -316,7 +316,6 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
if (!qdev_realize(DEVICE(xsrc), NULL, errp)) {
return;
}
sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xsrc->esb_mmio);
/*
* Initialize the END ESB source
@ -328,7 +327,6 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
if (!qdev_realize(DEVICE(end_xsrc), NULL, errp)) {
return;
}
sysbus_init_mmio(SYS_BUS_DEVICE(xive), &end_xsrc->esb_mmio);
/* Set the mapping address of the END ESB pages after the source ESBs */
xive->end_base = xive->vc_base + xive_source_esb_len(xsrc);
@ -347,15 +345,17 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)
/* TIMA initialization */
memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &spapr_xive_tm_ops,
xive, "xive.tima", 4ull << TM_SHIFT);
sysbus_init_mmio(SYS_BUS_DEVICE(xive), &xive->tm_mmio);
/*
* Map all regions. These will be enabled or disabled at reset and
* can also be overridden by KVM memory regions if active
*/
sysbus_mmio_map(SYS_BUS_DEVICE(xive), 0, xive->vc_base);
sysbus_mmio_map(SYS_BUS_DEVICE(xive), 1, xive->end_base);
sysbus_mmio_map(SYS_BUS_DEVICE(xive), 2, xive->tm_base);
memory_region_add_subregion(get_system_memory(), xive->vc_base,
&xsrc->esb_mmio);
memory_region_add_subregion(get_system_memory(), xive->end_base,
&end_xsrc->esb_mmio);
memory_region_add_subregion(get_system_memory(), xive->tm_base,
&xive->tm_mmio);
}
static int spapr_xive_get_eas(XiveRouter *xrtr, uint8_t eas_blk,

5
hw/isa/i82378.c
View File

@ -67,6 +67,7 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
uint8_t *pci_conf;
ISABus *isabus;
ISADevice *pit;
ISADevice *pcspk;
pci_conf = pci->config;
pci_set_word(pci_conf + PCI_COMMAND,
@ -102,7 +103,9 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
pit = i8254_pit_init(isabus, 0x40, 0, NULL);
/* speaker */
pcspk_init(isa_new(TYPE_PC_SPEAKER), isabus, pit);
pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal);
isa_realize_and_unref(pcspk, isabus, &error_fatal);
/* 2 82C37 (dma) */
isa_create_simple(isabus, "i82374");

11
hw/isa/isa-bus.c
View File

@ -52,18 +52,25 @@ static const TypeInfo isa_bus_info = {
ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
MemoryRegion *address_space_io, Error **errp)
{
DeviceState *bridge = NULL;
if (isabus) {
error_setg(errp, "Can't create a second ISA bus");
return NULL;
}
if (!dev) {
dev = qdev_new("isabus-bridge");
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
bridge = qdev_new("isabus-bridge");
dev = bridge;
}
isabus = ISA_BUS(qbus_new(TYPE_ISA_BUS, dev, NULL));
isabus->address_space = address_space;
isabus->address_space_io = address_space_io;
if (bridge) {
sysbus_realize_and_unref(SYS_BUS_DEVICE(bridge), &error_fatal);
}
return isabus;
}

2
hw/loongarch/virt.c
View File

@ -412,6 +412,7 @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState
}
dev = qdev_new(TYPE_ACPI_GED);
qdev_prop_set_uint32(dev, "ged-event", event);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* ged event */
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR);
@ -422,7 +423,6 @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev;
}

1
hw/mips/cps.c
View File

@ -24,7 +24,6 @@
#include "hw/mips/mips.h"
#include "hw/qdev-clock.h"
#include "hw/qdev-properties.h"
#include "hw/mips/cpudevs.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"

1
hw/mips/fuloong2e.c
View File

@ -30,7 +30,6 @@
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/bootloader.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "hw/loader.h"
#include "hw/ide/pci.h"

6
hw/mips/jazz.c
View File

@ -26,7 +26,6 @@
#include "qemu/datadir.h"
#include "hw/clock.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/intc/i8259.h"
#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
@ -177,6 +176,7 @@ static void mips_jazz_init(MachineState *machine,
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
ISADevice *pcspk;
DriveInfo *fds[MAX_FD];
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
@ -279,7 +279,9 @@ static void mips_jazz_init(MachineState *machine,
isa_bus_register_input_irqs(isa_bus, i8259);
i8257_dma_init(isa_bus, 0);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);
pcspk = isa_new(TYPE_PC_SPEAKER);
object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal);
isa_realize_and_unref(pcspk, isa_bus, &error_fatal);
/* Video card */
switch (jazz_model) {

1
hw/mips/loongson3_virt.c
View File

@ -32,7 +32,6 @@
#include "hw/char/serial.h"
#include "hw/intc/loongson_liointc.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/mips/fw_cfg.h"
#include "hw/mips/loongson3_bootp.h"
#include "hw/misc/unimp.h"

3
hw/mips/malta.c
View File

@ -37,7 +37,6 @@
#include "hw/block/flash.h"
#include "hw/mips/mips.h"
#include "hw/mips/bootloader.h"
#include "hw/mips/cpudevs.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "qemu/log.h"
@ -206,7 +205,7 @@ static eeprom24c0x_t spd_eeprom = {
static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
{
enum { SDR = 0x4, DDR2 = 0x8 } type;
enum sdram_type type;
uint8_t *spd = spd_eeprom.contents;
uint8_t nbanks = 0;
uint16_t density = 0;

1
hw/mips/mips_int.c
View File

@ -23,7 +23,6 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "hw/irq.h"
#include "hw/mips/cpudevs.h"
#include "sysemu/kvm.h"
#include "kvm_mips.h"

1
hw/mips/mipssim.c
View File

@ -30,7 +30,6 @@
#include "qemu/datadir.h"
#include "hw/clock.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/char/serial.h"
#include "hw/isa/isa.h"
#include "net/net.h"

20
hw/misc/allwinner-r40-dramc.c
View File

@ -421,19 +421,23 @@ static void allwinner_r40_dramc_realize(DeviceState *dev, Error **errp)
exit(1);
}
/* detect_cells */
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s), 3, s->ram_addr, 10);
/* R40 support max 2G memory but we only support up to 1G now. */
memory_region_init_io(&s->detect_cells, OBJECT(s),
&allwinner_r40_detect_ops, s,
"DRAMCELLS", 1 * GiB);
memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
&s->detect_cells, 10);
memory_region_set_enabled(&s->detect_cells, false);
/*
* We only support DRAM size up to 1G now, so prepare a high memory page
* after 1G for dualrank detect. index = 4
* after 1G for dualrank detect.
*/
memory_region_init_io(&s->dram_high, OBJECT(s),
&allwinner_r40_dualrank_detect_ops, s,
"DRAMHIGH", KiB);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->dram_high);
sysbus_mmio_map(SYS_BUS_DEVICE(s), 4, s->ram_addr + GiB);
memory_region_add_subregion(get_system_memory(), s->ram_addr + GiB,
&s->dram_high);
}
static void allwinner_r40_dramc_init(Object *obj)
@ -458,12 +462,6 @@ static void allwinner_r40_dramc_init(Object *obj)
&allwinner_r40_dramphy_ops, s,
"DRAMPHY", 4 * KiB);
sysbus_init_mmio(sbd, &s->dramphy_iomem);
/* R40 support max 2G memory but we only support up to 1G now. index 3 */
memory_region_init_io(&s->detect_cells, OBJECT(s),
&allwinner_r40_detect_ops, s,
"DRAMCELLS", 1 * GiB);
sysbus_init_mmio(sbd, &s->detect_cells);
}
static Property allwinner_r40_dramc_properties[] = {

4
hw/misc/mips_itu.c
View File

@ -532,7 +532,7 @@ static void mips_itu_realize(DeviceState *dev, Error **errp)
return;
}
env = &s->cpu0->env;
env = &MIPS_CPU(s->cpu0)->env;
if (env->saarp) {
s->saar = env->CP0_SAAR;
}
@ -563,7 +563,7 @@ static Property mips_itu_properties[] = {
ITC_FIFO_NUM_MAX),
DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,
ITC_SEMAPH_NUM_MAX),
DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU *),
DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, ArchCPU *),
DEFINE_PROP_END_OF_LIST(),
};

7
hw/net/cadence_gem.c
View File

@ -1654,11 +1654,6 @@ static void gem_init(Object *obj)
"enet", sizeof(s->regs));
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
(Object **)&s->dma_mr,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_STRONG);
}
static const VMStateDescription vmstate_cadence_gem = {
@ -1691,6 +1686,8 @@ static Property gem_properties[] = {
num_type2_screeners, 4),
DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
jumbo_max_len, 10240),
DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};

30
hw/pci-host/bonito.c
View File

@ -654,7 +654,7 @@ static void bonito_host_realize(DeviceState *dev, Error **errp)
static void bonito_pci_realize(PCIDevice *dev, Error **errp)
{
PCIBonitoState *s = PCI_BONITO(dev);
SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
MemoryRegion *host_mem = get_system_memory();
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
BonitoState *bs = s->pcihost;
MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
@ -668,48 +668,45 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
/* set the north bridge register mapping */
memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
"north-bridge-register", BONITO_INTERNAL_REG_SIZE);
sysbus_init_mmio(sysbus, &s->iomem);
sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
memory_region_add_subregion(host_mem, BONITO_INTERNAL_REG_BASE, &s->iomem);
/* set the north bridge pci configure mapping */
memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
"north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
sysbus_init_mmio(sysbus, &phb->conf_mem);
sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
memory_region_add_subregion(host_mem, BONITO_PCICONFIG_BASE,
&phb->conf_mem);
/* set the south bridge pci configure mapping */
memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
"south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
sysbus_init_mmio(sysbus, &phb->data_mem);
sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
memory_region_add_subregion(host_mem, BONITO_SPCICONFIG_BASE,
&phb->data_mem);
create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
"ldma", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_ldma);
sysbus_mmio_map(sysbus, 3, 0x1fe00200);
memory_region_add_subregion(host_mem, 0x1fe00200, &s->iomem_ldma);
/* PCI copier */
memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
"cop", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_cop);
sysbus_mmio_map(sysbus, 4, 0x1fe00300);
memory_region_add_subregion(host_mem, 0x1fe00300, &s->iomem_cop);
create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB);
/* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
get_system_io(), 0, BONITO_PCIIO_SIZE);
sysbus_init_mmio(sysbus, &s->bonito_pciio);
sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
memory_region_add_subregion(host_mem, BONITO_PCIIO_BASE,
&s->bonito_pciio);
/* add pci local io mapping */
memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]",
get_system_io(), 0, 256 * KiB);
sysbus_init_mmio(sysbus, &s->bonito_localio);
sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
memory_region_add_subregion(host_mem, BONITO_DEV_BASE,
&s->bonito_localio);
create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB,
256 * KiB);
create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB,
@ -719,8 +716,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
&bs->pci_mem, 0, BONITO_PCIHI_SIZE);
memory_region_add_subregion(get_system_memory(),
BONITO_PCIHI_BASE, pcimem_alias);
memory_region_add_subregion(host_mem, BONITO_PCIHI_BASE, pcimem_alias);
create_unimplemented_device("PCI_2",
(hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
2 * GiB);

57
hw/pci-host/sh_pci.c
View File

@ -40,7 +40,7 @@ struct SHPCIState {
PCIHostState parent_obj;
PCIDevice *dev;
qemu_irq irq[4];
qemu_irq irq[PCI_NUM_PINS];
MemoryRegion memconfig_p4;
MemoryRegion memconfig_a7;
MemoryRegion isa;
@ -116,7 +116,7 @@ static void sh_pci_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
static void sh_pci_device_realize(DeviceState *dev, Error **errp)
static void sh_pcic_host_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
SHPCIState *s = SH_PCI_HOST_BRIDGE(dev);
@ -131,7 +131,8 @@ static void sh_pci_device_realize(DeviceState *dev, Error **errp)
s->irq,
get_system_memory(),
get_system_io(),
PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
PCI_DEVFN(0, 0), PCI_NUM_PINS,
TYPE_PCI_BUS);
memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s,
"sh_pci", 0x224);
memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2",
@ -145,19 +146,19 @@ static void sh_pci_device_realize(DeviceState *dev, Error **errp)
s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
}
static void sh_pci_host_realize(PCIDevice *d, Error **errp)
static void sh_pcic_pci_realize(PCIDevice *d, Error **errp)
{
pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
}
static void sh_pci_host_class_init(ObjectClass *klass, void *data)
static void sh_pcic_pci_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
k->realize = sh_pci_host_realize;
k->realize = sh_pcic_pci_realize;
k->vendor_id = PCI_VENDOR_ID_HITACHI;
k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R;
/*
@ -167,35 +168,29 @@ static void sh_pci_host_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
static const TypeInfo sh_pci_host_info = {
.name = "sh_pci_host",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
.class_init = sh_pci_host_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
};
static void sh_pci_device_class_init(ObjectClass *klass, void *data)
static void sh_pcic_host_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = sh_pci_device_realize;
dc->realize = sh_pcic_host_realize;
}
static const TypeInfo sh_pci_device_info = {
.name = TYPE_SH_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(SHPCIState),
.class_init = sh_pci_device_class_init,
static const TypeInfo sh_pcic_types[] = {
{
.name = TYPE_SH_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(SHPCIState),
.class_init = sh_pcic_host_class_init,
}, {
.name = "sh_pci_host",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIDevice),
.class_init = sh_pcic_pci_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
{ },
},
},
};
static void sh_pci_register_types(void)
{
type_register_static(&sh_pci_device_info);
type_register_static(&sh_pci_host_info);
}
type_init(sh_pci_register_types)
DEFINE_TYPES(sh_pcic_types)

25
hw/pci/pci.c
View File

@ -500,15 +500,14 @@ bool pci_bus_bypass_iommu(PCIBus *bus)
}
static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
MemoryRegion *mem, MemoryRegion *io,
uint8_t devfn_min)
{
assert(PCI_FUNC(devfn_min) == 0);
bus->devfn_min = devfn_min;
bus->slot_reserved_mask = 0x0;
bus->address_space_mem = address_space_mem;
bus->address_space_io = address_space_io;
bus->address_space_mem = mem;
bus->address_space_io = io;
bus->flags |= PCI_BUS_IS_ROOT;
/* host bridge */
@ -529,25 +528,21 @@ bool pci_bus_is_express(const PCIBus *bus)
void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
const char *name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
MemoryRegion *mem, MemoryRegion *io,
uint8_t devfn_min, const char *typename)
{
qbus_init(bus, bus_size, typename, parent, name);
pci_root_bus_internal_init(bus, parent, address_space_mem,
address_space_io, devfn_min);
pci_root_bus_internal_init(bus, parent, mem, io, devfn_min);
}
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
MemoryRegion *mem, MemoryRegion *io,
uint8_t devfn_min, const char *typename)
{
PCIBus *bus;
bus = PCI_BUS(qbus_new(typename, parent, name));
pci_root_bus_internal_init(bus, parent, address_space_mem,
address_space_io, devfn_min);
pci_root_bus_internal_init(bus, parent, mem, io, devfn_min);
return bus;
}
@ -586,15 +581,13 @@ void pci_bus_irqs_cleanup(PCIBus *bus)
PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
MemoryRegion *mem, MemoryRegion *io,
uint8_t devfn_min, int nirq,
const char *typename)
{
PCIBus *bus;
bus = pci_root_bus_new(parent, name, address_space_mem,
address_space_io, devfn_min, typename);
bus = pci_root_bus_new(parent, name, mem, io, devfn_min, typename);
pci_bus_irqs(bus, set_irq, irq_opaque, nirq);
pci_bus_map_irqs(bus, map_irq);
return bus;

26
hw/ppc/pnv.c
View File

@ -1217,10 +1217,9 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
name = g_strdup_printf("icp-%x", chip->chip_id);
memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
g_free(name);
sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip),
&chip8->icp_mmio);
/* Map the ICP registers for each thread */
for (i = 0; i < chip->nr_cores; i++) {
@ -1249,12 +1248,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
assert(chip8->xics);
/* XSCOM bridge is first */
pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip));
pcc->parent_realize(dev, &local_err);
if (local_err) {
@ -1512,12 +1506,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
Error *local_err = NULL;
/* XSCOM bridge is first */
pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip));
pcc->parent_realize(dev, &local_err);
if (local_err) {
@ -1727,12 +1716,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
Error *local_err = NULL;
/* XSCOM bridge is first */
pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip));
pcc->parent_realize(dev, &local_err);
if (local_err) {

5
hw/ppc/pnv_xscom.c
View File

@ -221,15 +221,14 @@ const MemoryRegionOps pnv_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp)
void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
char *name;
name = g_strdup_printf("xscom-%x", chip->chip_id);
memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
chip, name, size);
sysbus_init_mmio(sbd, &chip->xscom_mmio);
memory_region_add_subregion(get_system_memory(), addr, &chip->xscom_mmio);
memory_region_init(&chip->xscom, OBJECT(chip), name, size);
address_space_init(&chip->xscom_as, &chip->xscom, name);

3
hw/ppc/spapr_vio.c
View File

@ -574,13 +574,14 @@ SpaprVioBus *spapr_vio_bus_init(void)
/* Create bridge device */
dev = qdev_new(TYPE_SPAPR_VIO_BRIDGE);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
qbus = qbus_new(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
bus = SPAPR_VIO_BUS(qbus);
bus->next_reg = SPAPR_VIO_REG_BASE;
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* hcall-vio */
spapr_register_hypercall(H_VIO_SIGNAL, h_vio_signal);

7
hw/s390x/css-bridge.c
View File

@ -95,7 +95,6 @@ static const TypeInfo virtual_css_bus_info = {
VirtualCssBus *virtual_css_bus_init(void)
{
VirtualCssBus *cbus;
BusState *bus;
DeviceState *dev;
@ -103,19 +102,19 @@ VirtualCssBus *virtual_css_bus_init(void)
dev = qdev_new(TYPE_VIRTUAL_CSS_BRIDGE);
object_property_add_child(qdev_get_machine(), TYPE_VIRTUAL_CSS_BRIDGE,
OBJECT(dev));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* Create bus on bridge device */
bus = qbus_new(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
cbus = VIRTUAL_CSS_BUS(bus);
/* Enable hotplugging */
qbus_set_hotplug_handler(bus, OBJECT(dev));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
css_register_io_adapters(CSS_IO_ADAPTER_VIRTIO, true, false,
0, &error_abort);
return cbus;
return VIRTUAL_CSS_BUS(bus);
}
/***************** Virtual-css Bus Bridge Device ********************/

8
hw/s390x/sclpquiesce.c
View File

@ -78,12 +78,10 @@ static const VMStateDescription vmstate_sclpquiesce = {
}
};
typedef struct QuiesceNotifier QuiesceNotifier;
static struct QuiesceNotifier {
typedef struct QuiesceNotifier {
Notifier notifier;
SCLPEvent *event;
} qn;
} QuiesceNotifier;
static void quiesce_powerdown_req(Notifier *n, void *opaque)
{
@ -97,6 +95,8 @@ static void quiesce_powerdown_req(Notifier *n, void *opaque)
static int quiesce_init(SCLPEvent *event)
{
static QuiesceNotifier qn;
qn.notifier.notify = quiesce_powerdown_req;
qn.event = event;

2
hw/scsi/virtio-scsi.c
View File

@ -761,7 +761,7 @@ static void virtio_scsi_fail_cmd_req(VirtIOSCSIReq *req)
static int virtio_scsi_handle_cmd_req_prepare(VirtIOSCSI *s, VirtIOSCSIReq *req)
{
VirtIOSCSICommon *vs = &s->parent_obj;
VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(s);
SCSIDevice *d;
int rc;

15
hw/sd/sdhci.c
View File

@ -321,6 +321,8 @@ static void sdhci_poweron_reset(DeviceState *dev)
static void sdhci_data_transfer(void *opaque);
#define BLOCK_SIZE_MASK (4 * KiB - 1)
static void sdhci_send_command(SDHCIState *s)
{
SDRequest request;
@ -371,7 +373,8 @@ static void sdhci_send_command(SDHCIState *s)
sdhci_update_irq(s);
if (!timeout && s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
if (!timeout && (s->blksize & BLOCK_SIZE_MASK) &&
(s->cmdreg & SDHC_CMD_DATA_PRESENT)) {
s->data_count = 0;
sdhci_data_transfer(s);
}
@ -406,7 +409,6 @@ static void sdhci_end_transfer(SDHCIState *s)
/*
* Programmed i/o data transfer
*/
#define BLOCK_SIZE_MASK (4 * KiB - 1)
/* Fill host controller's read buffer with BLKSIZE bytes of data from card */
static void sdhci_read_block_from_card(SDHCIState *s)
@ -1154,7 +1156,8 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
s->sdmasysad = (s->sdmasysad & mask) | value;
MASKED_WRITE(s->sdmasysad, mask, value);
/* Writing to last byte of sdmasysad might trigger transfer */
if (!(mask & 0xFF000000) && s->blkcnt && s->blksize &&
if (!(mask & 0xFF000000) && s->blkcnt &&
(s->blksize & BLOCK_SIZE_MASK) &&
SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
if (s->trnmod & SDHC_TRNS_MULTI) {
sdhci_sdma_transfer_multi_blocks(s);
@ -1168,7 +1171,11 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
if (!TRANSFERRING_DATA(s->prnsts)) {
uint16_t blksize = s->blksize;
MASKED_WRITE(s->blksize, mask, extract32(value, 0, 12));
/*
* [14:12] SDMA Buffer Boundary
* [11:00] Transfer Block Size
*/
MASKED_WRITE(s->blksize, mask, extract32(value, 0, 15));
MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16);
/* Limit block size to the maximum buffer size */

8
hw/sparc64/sun4u.c
View File

@ -360,11 +360,11 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
pci_dev->config[0x09] = 0x00; // programming i/f
pci_dev->config[0x0D] = 0x0a; // latency_timer
memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
0, 0x1000000);
memory_region_init_alias(&s->bar0, OBJECT(s), "bar0",
pci_address_space_io(pci_dev), 0, 0x1000000);
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
0, 0x8000);
memory_region_init_alias(&s->bar1, OBJECT(s), "bar1",
pci_address_space_io(pci_dev), 0, 0x8000);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
}

5
hw/virtio/virtio-pmem.c
View File

@ -147,10 +147,7 @@ static void virtio_pmem_fill_device_info(const VirtIOPMEM *pmem,
static MemoryRegion *virtio_pmem_get_memory_region(VirtIOPMEM *pmem,
Error **errp)
{
if (!pmem->memdev) {
error_setg(errp, "'%s' property must be set", VIRTIO_PMEM_MEMDEV_PROP);
return NULL;
}
assert(pmem->memdev);
return &pmem->memdev->mr;
}

2
include/hw/acpi/pcihp.h
View File

@ -56,7 +56,7 @@ typedef struct AcpiPciHpState {
} AcpiPciHpState;
void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root,
MemoryRegion *address_space_io, uint16_t io_base);
MemoryRegion *io, uint16_t io_base);
bool acpi_pcihp_is_hotpluggbale_bus(AcpiPciHpState *s, BusState *bus);
void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev,

10
include/hw/audio/pcspk.h
View File

@ -25,16 +25,6 @@
#ifndef HW_PCSPK_H
#define HW_PCSPK_H
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
#define TYPE_PC_SPEAKER "isa-pcspk"
static inline void pcspk_init(ISADevice *isadev, ISABus *bus, ISADevice *pit)
{
object_property_set_link(OBJECT(isadev), "pit", OBJECT(pit), NULL);
isa_realize_and_unref(isadev, bus, &error_fatal);
}
#endif /* HW_PCSPK_H */

4
include/hw/core/cpu.h
View File

@ -618,8 +618,10 @@ bool cpu_paging_enabled(const CPUState *cpu);
* @cpu: The CPU whose memory mappings are to be obtained.
* @list: Where to write the memory mappings to.
* @errp: Pointer for reporting an #Error.
*
* Returns: %true on success, %false otherwise.
*/
void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp);
#if !defined(CONFIG_USER_ONLY)

2
include/hw/core/sysemu-cpu-ops.h
View File

@ -19,7 +19,7 @@ typedef struct SysemuCPUOps {
/**
* @get_memory_mapping: Callback for obtaining the memory mappings.
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
bool (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
/**
* @get_paging_enabled: Callback for inquiring whether paging is enabled.

14
include/hw/mips/cpudevs.h
View File

@ -1,14 +0,0 @@
#ifndef HW_MIPS_CPUDEVS_H
#define HW_MIPS_CPUDEVS_H
#include "target/mips/cpu-qom.h"
/* Definitions for MIPS CPU internal devices. */
/* mips_int.c */
void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
/* mips_timer.c */
void cpu_mips_clock_init(MIPSCPU *cpu);
#endif

4
include/hw/misc/mips_itu.h
View File

@ -73,10 +73,12 @@ struct MIPSITUState {
/* SAAR */
uint64_t *saar;
MIPSCPU *cpu0;
ArchCPU *cpu0;
};
/* Get ITC Configuration Tag memory region. */
MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu);
void itc_reconfigure(struct MIPSITUState *tag);
#endif /* MIPS_ITU_H */

9
include/hw/pci/pci.h
View File

@ -279,12 +279,10 @@ bool pci_bus_is_express(const PCIBus *bus);
void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
const char *name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
MemoryRegion *mem, MemoryRegion *io,
uint8_t devfn_min, const char *typename);
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
MemoryRegion *mem, MemoryRegion *io,
uint8_t devfn_min, const char *typename);
void pci_root_bus_cleanup(PCIBus *bus);
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
@ -304,8 +302,7 @@ int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
MemoryRegion *mem, MemoryRegion *io,
uint8_t devfn_min, int nirq,
const char *typename);
void pci_unregister_root_bus(PCIBus *bus);

2
include/hw/ppc/pnv_xscom.h
View File

@ -170,7 +170,7 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */
#define PNV10_XSCOM_PEC_PCI_SIZE 0x200
void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
void pnv_xscom_init(PnvChip *chip, uint64_t size, hwaddr addr);
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
uint64_t xscom_base, uint64_t xscom_size,
const char *compat, int compat_size);

2
include/hw/virtio/virtio-input.h
View File

@ -84,7 +84,7 @@ struct VirtIOInputHID {
VirtIOInput parent_obj;
char *display;
uint32_t head;
QemuInputHandler *handler;
const QemuInputHandler *handler;
QemuInputHandlerState *hs;
int ledstate;
bool wheel_axis;

2
include/sysemu/memory_mapping.h
View File

@ -71,7 +71,7 @@ void guest_phys_blocks_free(GuestPhysBlockList *list);
void guest_phys_blocks_init(GuestPhysBlockList *list);
void guest_phys_blocks_append(GuestPhysBlockList *list);
void qemu_get_guest_memory_mapping(MemoryMappingList *list,
bool qemu_get_guest_memory_mapping(MemoryMappingList *list,
const GuestPhysBlockList *guest_phys_blocks,
Error **errp);

2
include/ui/input.h
View File

@ -30,7 +30,7 @@ struct QemuInputHandler {
};
QemuInputHandlerState *qemu_input_handler_register(DeviceState *dev,
QemuInputHandler *handler);
const QemuInputHandler *handler);
void qemu_input_handler_activate(QemuInputHandlerState *s);
void qemu_input_handler_deactivate(QemuInputHandlerState *s);
void qemu_input_handler_unregister(QemuInputHandlerState *s);

6
meson.build
View File

@ -4087,8 +4087,10 @@ if 'cpp' in all_languages
else
summary_info += {'C++ compiler': false}
endif
if targetos == 'darwin'
if 'objc' in all_languages
summary_info += {'Objective-C compiler': ' '.join(meson.get_compiler('objc').cmd_array())}
else
summary_info += {'Objective-C compiler': false}
endif
option_cflags = (get_option('debug') ? ['-g'] : [])
if get_option('optimization') != 'plain'
@ -4098,7 +4100,7 @@ summary_info += {'CFLAGS': ' '.join(get_option('c_args') + option_cfl
if 'cpp' in all_languages
summary_info += {'CXXFLAGS': ' '.join(get_option('cpp_args') + option_cflags)}
endif
if targetos == 'darwin'
if 'objc' in all_languages
summary_info += {'OBJCFLAGS': ' '.join(get_option('objc_args') + option_cflags)}
endif
link_args = get_option('c_link_args')

17
system/memory_mapping.c
View File

@ -291,7 +291,7 @@ void guest_phys_blocks_append(GuestPhysBlockList *list)
memory_listener_unregister(&g.listener);
}
static CPUState *find_paging_enabled_cpu(CPUState *start_cpu)
static CPUState *find_paging_enabled_cpu(void)
{
CPUState *cpu;
@ -304,26 +304,24 @@ static CPUState *find_paging_enabled_cpu(CPUState *start_cpu)
return NULL;
}
void qemu_get_guest_memory_mapping(MemoryMappingList *list,
bool qemu_get_guest_memory_mapping(MemoryMappingList *list,
const GuestPhysBlockList *guest_phys_blocks,
Error **errp)
{
ERRP_GUARD();
CPUState *cpu, *first_paging_enabled_cpu;
GuestPhysBlock *block;
ram_addr_t offset, length;
first_paging_enabled_cpu = find_paging_enabled_cpu(first_cpu);
first_paging_enabled_cpu = find_paging_enabled_cpu();
if (first_paging_enabled_cpu) {
for (cpu = first_paging_enabled_cpu; cpu != NULL;
cpu = CPU_NEXT(cpu)) {
Error *err = NULL;
cpu_get_memory_mapping(cpu, list, &err);
if (err) {
error_propagate(errp, err);
return;
if (!cpu_get_memory_mapping(cpu, list, errp)) {
return false;
}
}
return;
return true;
}
/*
@ -335,6 +333,7 @@ void qemu_get_guest_memory_mapping(MemoryMappingList *list,
length = block->target_end - block->target_start;
create_new_memory_mapping(list, offset, offset, length);
}
return true;
}
void qemu_get_guest_simple_memory_mapping(MemoryMappingList *list,

6
target/i386/arch_memory_mapping.c
View File

@ -266,7 +266,7 @@ static void walk_pml5e(MemoryMappingList *list, AddressSpace *as,
}
#endif
void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
bool x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
@ -275,7 +275,7 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
if (!cpu_paging_enabled(cs)) {
/* paging is disabled */
return;
return true;
}
a20_mask = x86_get_a20_mask(env);
@ -310,5 +310,7 @@ void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
pse = !!(env->cr[4] & CR4_PSE_MASK);
walk_pde2(list, cs->as, pde_addr, a20_mask, pse);
}
return true;
}

2
target/i386/cpu.h
View File

@ -2055,7 +2055,7 @@ int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
DumpState *s);
void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);

7
target/mips/cpu.h
View File

@ -1345,11 +1345,10 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
#if !defined(CONFIG_USER_ONLY)
/* mips_int.c */
/* HW declaration specific to the MIPS target */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* mips_itu.c */
void itc_reconfigure(struct MIPSITUState *tag);
void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
void cpu_mips_clock_init(MIPSCPU *cpu);
#endif /* !CONFIG_USER_ONLY */

1
target/mips/sysemu/cp0_timer.c
View File

@ -22,7 +22,6 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/mips/cpudevs.h"
#include "qemu/timer.h"
#include "sysemu/kvm.h"
#include "internal.h"

1
target/mips/tcg/sysemu/cp0_helper.c
View File

@ -28,6 +28,7 @@
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "hw/misc/mips_itu.h"
/* SMP helpers. */

1
target/mips/tcg/sysemu/tlb_helper.c
View File

@ -24,7 +24,6 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "hw/mips/cpudevs.h"
#include "exec/helper-proto.h"
/* TLB management */

2
ui/input-legacy.c
View File

@ -127,7 +127,7 @@ static void legacy_kbd_event(DeviceState *dev, QemuConsole *src,
}
}
static QemuInputHandler legacy_kbd_handler = {
static const QemuInputHandler legacy_kbd_handler = {
.name = "legacy-kbd",
.mask = INPUT_EVENT_MASK_KEY,
.event = legacy_kbd_event,

4
ui/input.c
View File

@ -10,7 +10,7 @@
struct QemuInputHandlerState {
DeviceState *dev;
QemuInputHandler *handler;
const QemuInputHandler *handler;
int id;
int events;
QemuConsole *con;
@ -46,7 +46,7 @@ static uint32_t queue_count;
static uint32_t queue_limit = 1024;
QemuInputHandlerState *qemu_input_handler_register(DeviceState *dev,
QemuInputHandler *handler)
const QemuInputHandler *handler)
{
QemuInputHandlerState *s = g_new0(QemuInputHandlerState, 1);
static int id = 1;

2
ui/vdagent.c
View File

@ -297,7 +297,7 @@ static void vdagent_pointer_sync(DeviceState *dev)
}
}
static QemuInputHandler vdagent_mouse_handler = {
static const QemuInputHandler vdagent_mouse_handler = {
.name = "vdagent mouse",
.mask = INPUT_EVENT_MASK_BTN | INPUT_EVENT_MASK_ABS,
.event = vdagent_pointer_event,

18
util/cutils.c
View File

@ -1163,17 +1163,21 @@ char *get_relocated_path(const char *dir)
g_string_append(result, "/qemu-bundle");
if (access(result->str, R_OK) == 0) {
#ifdef G_OS_WIN32
size_t size = mbsrtowcs(NULL, &dir, 0, &(mbstate_t){0}) + 1;
const char *src = dir;
size_t size = mbsrtowcs(NULL, &src, 0, &(mbstate_t){0}) + 1;
PWSTR wdir = g_new(WCHAR, size);
mbsrtowcs(wdir, &dir, size, &(mbstate_t){0});
mbsrtowcs(wdir, &src, size, &(mbstate_t){0});
PCWSTR wdir_skipped_root;
PathCchSkipRoot(wdir, &wdir_skipped_root);
if (PathCchSkipRoot(wdir, &wdir_skipped_root) == S_OK) {
size = wcsrtombs(NULL, &wdir_skipped_root, 0, &(mbstate_t){0});
char *cursor = result->str + result->len;
g_string_set_size(result, result->len + size);
wcsrtombs(cursor, &wdir_skipped_root, size + 1, &(mbstate_t){0});
} else {
g_string_append(result, dir);
}
size = wcsrtombs(NULL, &wdir_skipped_root, 0, &(mbstate_t){0});
char *cursor = result->str + result->len;
g_string_set_size(result, result->len + size);
wcsrtombs(cursor, &wdir_skipped_root, size + 1, &(mbstate_t){0});
g_free(wdir);
#else
g_string_append(result, dir);