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target/riscv: Mark both sstatus and msstatus_hs as dirty 

Mark both sstatus and vsstatus as dirty (3).

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:02:46 -08:00 committed by Palmer Dabbelt
parent 29409c1d92
commit 45b4dc8b40
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 13 additions and 0 deletions
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13
target/riscv/translate.c
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@ -44,6 +44,8 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */ /* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn; target_ulong pc_succ_insn;
target_ulong priv_ver; target_ulong priv_ver;
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs; uint32_t mstatus_fs;
uint32_t misa; uint32_t misa;
uint32_t mem_idx; uint32_t mem_idx;
@ -395,6 +397,12 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
}
tcg_temp_free(tmp); tcg_temp_free(tmp);
} }
#else #else
@ -742,6 +750,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver; ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
#else
ctx->virt_enabled = false;
#endif
ctx->misa = env->misa; ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */ ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->ext_ifencei = cpu->cfg.ext_ifencei;