mirror of https://github.com/xemu-project/xemu.git
hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset
The reset value of IPIDR should be zero for Freescale chipset, per
the following 2 manuals I checked:
- P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
- P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
Currently it is set to 1, which leaves the IPI enabled on core 0
after power-on reset. Such may cause unexpected interrupt to be
delivered to core 0 if the IPI is triggered from core 0 to other
cores later.
Fixes: ffd5e9fe02
("openpic: Reset IRQ source private members")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20210918032653.646370-1-bin.meng@windriver.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
parent
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@ -1276,6 +1276,15 @@ static void openpic_reset(DeviceState *d)
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break;
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}
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/* Mask all IPI interrupts for Freescale OpenPIC */
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if ((opp->model == OPENPIC_MODEL_FSL_MPIC_20) ||
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(opp->model == OPENPIC_MODEL_FSL_MPIC_42)) {
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if (i >= opp->irq_ipi0 && i < opp->irq_tim0) {
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write_IRQreg_idr(opp, i, 0);
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continue;
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}
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}
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write_IRQreg_idr(opp, i, opp->idr_reset);
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}
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/* Initialise IRQ destinations */
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