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hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE 

In theory gsi base can start from 0 on loongarch virt machine,
however gsi base is hard-coded in linux kernel loongarch system,
else system fails to boot.

This patch renames macro PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE,
keeps value unchanged. GSI base is common concept in acpi spec
and easy to understand.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221228030719.991878-1-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Bibo Mao 2022-12-28 11:07:19 +08:00 committed by Song Gao
parent 262312d7ba
commit 456eb81f76
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 14 additions and 13 deletions
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2
hw/loongarch/acpi-build.c
View File

@ -271,7 +271,7 @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
.pio.size = VIRT_PCI_IO_SIZE, .pio.size = VIRT_PCI_IO_SIZE,
.ecam.base = VIRT_PCI_CFG_BASE, .ecam.base = VIRT_PCI_CFG_BASE,
.ecam.size = VIRT_PCI_CFG_SIZE, .ecam.size = VIRT_PCI_CFG_SIZE,
.irq = PCH_PIC_IRQ_OFFSET + VIRT_DEVICE_IRQS, .irq = VIRT_GSI_BASE + VIRT_DEVICE_IRQS,
.bus = lams->pci_bus, .bus = lams->pci_bus,
}; };

8
hw/loongarch/virt.c
View File

@ -432,7 +432,7 @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET)); qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
return dev; return dev;
} }
@ -452,7 +452,7 @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
sysbus = SYS_BUS_DEVICE(dev); sysbus = SYS_BUS_DEVICE(dev);
for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
irq = VIRT_PLATFORM_BUS_IRQ - PCH_PIC_IRQ_OFFSET + i; irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i;
sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq));
} }
@ -509,7 +509,7 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,
qdev_get_gpio_in(pch_pic, qdev_get_gpio_in(pch_pic,
VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET), VIRT_UART_IRQ - VIRT_GSI_BASE),
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
fdt_add_uart_node(lams); fdt_add_uart_node(lams);
@ -531,7 +531,7 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
qdev_get_gpio_in(pch_pic, qdev_get_gpio_in(pch_pic,
VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET)); VIRT_RTC_IRQ - VIRT_GSI_BASE));
fdt_add_rtc_node(lams); fdt_add_rtc_node(lams);
pm_mem = g_new(MemoryRegion, 1); pm_mem = g_new(MemoryRegion, 1);

17
include/hw/pci-host/ls7a.h
View File

@ -26,24 +26,25 @@
#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL #define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
/* /*
* According to the kernel pch irq start from 64 offset * GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot
* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs * 0 - 15 GSI for ISA devices even if there is no ISA devices
* used for pci device. * 16 - 63 GSI for CPU devices such as timers/perf monitor etc
* 64 - GSI for external devices
*/ */
#define VIRT_PCH_PIC_IRQ_NUM 32 #define VIRT_PCH_PIC_IRQ_NUM 32
#define PCH_PIC_IRQ_OFFSET 64 #define VIRT_GSI_BASE 64
#define VIRT_DEVICE_IRQS 16 #define VIRT_DEVICE_IRQS 16
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2) #define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)
#define VIRT_UART_BASE 0x1fe001e0 #define VIRT_UART_BASE 0x1fe001e0
#define VIRT_UART_SIZE 0X100 #define VIRT_UART_SIZE 0X100
#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3) #define VIRT_RTC_IRQ (VIRT_GSI_BASE + 3)
#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000) #define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100) #define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
#define VIRT_RTC_LEN 0x100 #define VIRT_RTC_LEN 0x100
#define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4) #define VIRT_SCI_IRQ (VIRT_GSI_BASE + 4)
#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 #define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000
#define VIRT_PLATFORM_BUS_SIZE 0x2000000 #define VIRT_PLATFORM_BUS_SIZE 0x2000000
#define VIRT_PLATFORM_BUS_NUM_IRQS 2 #define VIRT_PLATFORM_BUS_NUM_IRQS 2
#define VIRT_PLATFORM_BUS_IRQ 69 #define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 5)
#endif #endif