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hw/intc/arm_gicv3: Implement GICD_INMIR 

Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jinjie Ruan 2024-04-19 14:33:03 +01:00 committed by Peter Maydell
parent 7c79d98d2e
commit 44ed1e4b9a
2 changed files with 36 additions and 0 deletions
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34
hw/intc/arm_gicv3_dist.c
View File

@ -89,6 +89,29 @@ static int gicd_ns_access(GICv3State *s, int irq)
return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2); return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2);
} }
static void gicd_write_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
uint32_t *bmp, maskfn *maskfn,
int offset, uint32_t val)
{
/*
* Helper routine to implement writing to a "set" register
* (GICD_INMIR, etc).
* Semantics implemented here:
* RAZ/WI for SGIs, PPIs, unimplemented IRQs
* Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
* offset should be the offset in bytes of the register from the start
* of its group.
*/
int irq = offset * 8;
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
return;
}
val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
*gic_bmp_ptr32(bmp, irq) = val;
gicv3_update(s, irq, 32);
}
static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs, static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
uint32_t *bmp, uint32_t *bmp,
maskfn *maskfn, maskfn *maskfn,
@ -545,6 +568,11 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
/* RAZ/WI since affinity routing is always enabled */ /* RAZ/WI since affinity routing is always enabled */
*data = 0; *data = 0;
return true; return true;
case GICD_INMIR ... GICD_INMIR + 0x7f:
*data = (!s->nmi_support) ? 0 :
gicd_read_bitmap_reg(s, attrs, s->nmi, NULL,
offset - GICD_INMIR);
return true;
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
{ {
uint64_t r; uint64_t r;
@ -754,6 +782,12 @@ static bool gicd_writel(GICv3State *s, hwaddr offset,
case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf: case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
/* RAZ/WI since affinity routing is always enabled */ /* RAZ/WI since affinity routing is always enabled */
return true; return true;
case GICD_INMIR ... GICD_INMIR + 0x7f:
if (s->nmi_support) {
gicd_write_bitmap_reg(s, attrs, s->nmi, NULL,
offset - GICD_INMIR, value);
}
return true;
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf: case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
{ {
uint64_t r; uint64_t r;

2
hw/intc/gicv3_internal.h
View File

@ -52,6 +52,8 @@
#define GICD_SGIR 0x0F00 #define GICD_SGIR 0x0F00
#define GICD_CPENDSGIR 0x0F10 #define GICD_CPENDSGIR 0x0F10
#define GICD_SPENDSGIR 0x0F20 #define GICD_SPENDSGIR 0x0F20
#define GICD_INMIR 0x0F80
#define GICD_INMIRnE 0x3B00
#define GICD_IROUTER 0x6000 #define GICD_IROUTER 0x6000
#define GICD_IDREGS 0xFFD0 #define GICD_IDREGS 0xFFD0