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pcie: Use common ARI next function number 

Currently the only implementers of ARI is SR-IOV devices, and they
behave similar. Share the ARI next function number.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Message-Id: <20230710153838.33917-2-akihiko.odaki@daynix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Akihiko Odaki 2023-07-11 00:38:35 +09:00 committed by Michael S. Tsirkin
parent 661dee7bd0
commit 445416e301
6 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/pcie_sriov.txt
View File

@ -48,7 +48,7 @@ setting up a BAR for a VF.
... ...
int ret = pcie_endpoint_cap_init(d, 0x70); int ret = pcie_endpoint_cap_init(d, 0x70);
... ...
pcie_ari_init(d, 0x100, 1); pcie_ari_init(d, 0x100);
... ...
/* Add and initialize the SR/IOV capability */ /* Add and initialize the SR/IOV capability */
@ -78,7 +78,7 @@ setting up a BAR for a VF.
... ...
int ret = pcie_endpoint_cap_init(d, 0x60); int ret = pcie_endpoint_cap_init(d, 0x60);
... ...
pcie_ari_init(d, 0x100, 1); pcie_ari_init(d, 0x100);
... ...
memory_region_init(mr, ... ) memory_region_init(mr, ... )
pcie_sriov_vf_register_bar(d, bar_nr, mr); pcie_sriov_vf_register_bar(d, bar_nr, mr);

2
hw/net/igb.c
View File

@ -431,7 +431,7 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error **errp)
hw_error("Failed to initialize AER capability"); hw_error("Failed to initialize AER capability");
} }
pcie_ari_init(pci_dev, 0x150, 1); pcie_ari_init(pci_dev, 0x150);
pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, TYPE_IGBVF, pcie_sriov_pf_init(pci_dev, IGB_CAP_SRIOV_OFFSET, TYPE_IGBVF,
IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS, IGB_82576_VF_DEV_ID, IGB_MAX_VF_FUNCTIONS, IGB_MAX_VF_FUNCTIONS,

2
hw/net/igbvf.c
View File

@ -270,7 +270,7 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **errp)
hw_error("Failed to initialize AER capability"); hw_error("Failed to initialize AER capability");
} }
pcie_ari_init(dev, 0x150, 1); pcie_ari_init(dev, 0x150);
} }
static void igbvf_pci_uninit(PCIDevice *dev) static void igbvf_pci_uninit(PCIDevice *dev)

2
hw/nvme/ctrl.c
View File

@ -8120,7 +8120,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
pcie_endpoint_cap_init(pci_dev, 0x80); pcie_endpoint_cap_init(pci_dev, 0x80);
pcie_cap_flr_init(pci_dev); pcie_cap_flr_init(pci_dev);
if (n->params.sriov_max_vfs) { if (n->params.sriov_max_vfs) {
pcie_ari_init(pci_dev, 0x100, 1); pcie_ari_init(pci_dev, 0x100);
} }
/* add one to max_ioqpairs to account for the admin queue pair */ /* add one to max_ioqpairs to account for the admin queue pair */

4
hw/pci/pcie.c
View File

@ -1039,8 +1039,10 @@ void pcie_sync_bridge_lnk(PCIDevice *bridge_dev)
*/ */
/* ARI */ /* ARI */
void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn) void pcie_ari_init(PCIDevice *dev, uint16_t offset)
{ {
uint16_t nextfn = 1;
pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER, pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
offset, PCI_ARI_SIZEOF); offset, PCI_ARI_SIZEOF);
pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8); pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);

2
include/hw/pci/pcie.h
View File

@ -135,7 +135,7 @@ void pcie_sync_bridge_lnk(PCIDevice *dev);
void pcie_acs_init(PCIDevice *dev, uint16_t offset); void pcie_acs_init(PCIDevice *dev, uint16_t offset);
void pcie_acs_reset(PCIDevice *dev); void pcie_acs_reset(PCIDevice *dev);
void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); void pcie_ari_init(PCIDevice *dev, uint16_t offset);
void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num);
void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned); void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned);