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target/xtensa updates for 5.2: 

- add NMI support;
 - add DFPU option implementation;
 - update FPU tests to support both FPU2000 and DFPU;
 - add example cores with FPU2000 and DFPU.
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Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging

target/xtensa updates for 5.2:

- add NMI support;
- add DFPU option implementation;
- update FPU tests to support both FPU2000 and DFPU;
- add example cores with FPU2000 and DFPU.

# gpg: Signature made Fri 21 Aug 2020 21:09:37 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20200821-xtensa: (24 commits)
  target/xtensa: import DSP3400 core
  target/xtensa: import de233_fpu core
  tests/tcg/xtensa: add DFP0 arithmetic tests
  tests/tcg/xtensa: test double precision load/store
  tests/tcg/xtensa: add fp0 div and sqrt tests
  tests/tcg/xtensa: update test_lsc for DFPU
  tests/tcg/xtensa: update test_fp1 for DFPU
  tests/tcg/xtensa: update test_fp0_conv for DFPU
  tests/tcg/xtensa: expand madd tests
  tests/tcg/xtensa: update test_fp0_arith for DFPU
  tests/tcg/xtensa: fix test execution on ISS
  target/xtensa: implement FPU division and square root
  target/xtensa: add DFPU registers and opcodes
  target/xtensa: add DFPU option
  target/xtensa: don't access BR regfile directly
  target/xtensa: move FSR/FCR register accessors
  target/xtensa: rename FPU2000 translators and helpers
  target/xtensa: support copying registers up to 64 bits wide
  target/xtensa: add geometry to xtensa_get_regfile_by_name
  softfloat: add xtensa specialization for pickNaNMulAdd
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-08-24 19:55:23 +01:00
parent 30aa19446d c621b4142b
commit 44423107e7
33 changed files with 198894 additions and 837 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

286
fpu/softfloat-specialize.c.inc
View File

@ -79,12 +79,18 @@ this code that are retained.
* version 2 or later. See the COPYING file in the top-level directory.
*/
/* Define for architectures which deviate from IEEE in not supporting
/*
* Define whether architecture deviates from IEEE in not supporting
* signaling NaNs (so all NaNs are treated as quiet).
*/
static inline bool no_signaling_nans(float_status *status)
{
#if defined(TARGET_XTENSA)
#define NO_SIGNALING_NANS 1
return status->no_signaling_nans;
#else
return false;
#endif
}
/* Define how the architecture discriminates signaling NaNs.
* This done with the most significant bit of the fraction.
@ -111,12 +117,12 @@ static inline bool snan_bit_is_one(float_status *status)
static bool parts_is_snan_frac(uint64_t frac, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return false;
#else
bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
return msb == snan_bit_is_one(status);
#endif
if (no_signaling_nans(status)) {
return false;
} else {
bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
return msb == snan_bit_is_one(status);
}
}
/*----------------------------------------------------------------------------
@ -170,9 +176,8 @@ static FloatParts parts_default_nan(float_status *status)
static FloatParts parts_silence_nan(FloatParts a, float_status *status)
{
#ifdef NO_SIGNALING_NANS
g_assert_not_reached();
#elif defined(TARGET_HPPA)
g_assert(!no_signaling_nans(status));
#if defined(TARGET_HPPA)
a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
#else
@ -247,16 +252,17 @@ typedef struct {
bool float16_is_quiet_nan(float16 a_, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return float16_is_any_nan(a_);
#else
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
if (no_signaling_nans(status)) {
return float16_is_any_nan(a_);
} else {
return ((a >> 9) & 0x3F) == 0x3F;
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
} else {
return ((a >> 9) & 0x3F) == 0x3F;
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -266,16 +272,16 @@ bool float16_is_quiet_nan(float16 a_, float_status *status)
bool float16_is_signaling_nan(float16 a_, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return 0;
#else
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
return ((a >> 9) & 0x3F) == 0x3F;
if (no_signaling_nans(status)) {
return 0;
} else {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
uint16_t a = float16_val(a_);
if (snan_bit_is_one(status)) {
return ((a >> 9) & 0x3F) == 0x3F;
} else {
return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -285,16 +291,16 @@ bool float16_is_signaling_nan(float16 a_, float_status *status)
bool float32_is_quiet_nan(float32 a_, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return float32_is_any_nan(a_);
#else
uint32_t a = float32_val(a_);
if (snan_bit_is_one(status)) {
return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
if (no_signaling_nans(status)) {
return float32_is_any_nan(a_);
} else {
return ((uint32_t)(a << 1) >= 0xFF800000);
uint32_t a = float32_val(a_);
if (snan_bit_is_one(status)) {
return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
} else {
return ((uint32_t)(a << 1) >= 0xFF800000);
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -304,16 +310,16 @@ bool float32_is_quiet_nan(float32 a_, float_status *status)
bool float32_is_signaling_nan(float32 a_, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return 0;
#else
uint32_t a = float32_val(a_);
if (snan_bit_is_one(status)) {
return ((uint32_t)(a << 1) >= 0xFF800000);
if (no_signaling_nans(status)) {
return 0;
} else {
return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
uint32_t a = float32_val(a_);
if (snan_bit_is_one(status)) {
return ((uint32_t)(a << 1) >= 0xFF800000);
} else {
return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -374,7 +380,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
*----------------------------------------------------------------------------*/
static int pickNaN(FloatClass a_cls, FloatClass b_cls,
bool aIsLargerSignificand)
bool aIsLargerSignificand, float_status *status)
{
#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA)
/* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
@ -407,7 +413,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
} else {
return 1;
}
#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K)
#elif defined(TARGET_PPC) || defined(TARGET_M68K)
/* PowerPC propagation rules:
* 1. A if it sNaN or qNaN
* 2. B if it sNaN or qNaN
@ -432,6 +438,24 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
} else {
return 1;
}
#elif defined(TARGET_XTENSA)
/*
* Xtensa has two NaN propagation modes.
* Which one is active is controlled by float_status::use_first_nan.
*/
if (status->use_first_nan) {
if (is_nan(a_cls)) {
return 0;
} else {
return 1;
}
} else {
if (is_nan(b_cls)) {
return 1;
} else {
return 0;
}
}
#else
/* This implements x87 NaN propagation rules:
* SNaN + QNaN => return the QNaN
@ -562,6 +586,32 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
} else {
return 1;
}
#elif defined(TARGET_XTENSA)
/*
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
* an input NaN if we have one (ie c).
*/
if (infzero) {
float_raise(float_flag_invalid, status);
return 2;
}
if (status->use_first_nan) {
if (is_nan(a_cls)) {
return 0;
} else if (is_nan(b_cls)) {
return 1;
} else {
return 2;
}
} else {
if (is_nan(c_cls)) {
return 2;
} else if (is_nan(b_cls)) {
return 1;
} else {
return 0;
}
}
#else
/* A default implementation: prefer a to b to c.
* This is unlikely to actually match any real implementation.
@ -619,7 +669,7 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
aIsLargerSignificand = (av < bv) ? 1 : 0;
}
if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
if (is_snan(b_cls)) {
return float32_silence_nan(b, status);
}
@ -639,17 +689,17 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
bool float64_is_quiet_nan(float64 a_, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return float64_is_any_nan(a_);
#else
uint64_t a = float64_val(a_);
if (snan_bit_is_one(status)) {
return (((a >> 51) & 0xFFF) == 0xFFE)
&& (a & 0x0007FFFFFFFFFFFFULL);
if (no_signaling_nans(status)) {
return float64_is_any_nan(a_);
} else {
return ((a << 1) >= 0xFFF0000000000000ULL);
uint64_t a = float64_val(a_);
if (snan_bit_is_one(status)) {
return (((a >> 51) & 0xFFF) == 0xFFE)
&& (a & 0x0007FFFFFFFFFFFFULL);
} else {
return ((a << 1) >= 0xFFF0000000000000ULL);
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -659,17 +709,17 @@ bool float64_is_quiet_nan(float64 a_, float_status *status)
bool float64_is_signaling_nan(float64 a_, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return 0;
#else
uint64_t a = float64_val(a_);
if (snan_bit_is_one(status)) {
return ((a << 1) >= 0xFFF0000000000000ULL);
if (no_signaling_nans(status)) {
return 0;
} else {
return (((a >> 51) & 0xFFF) == 0xFFE)
&& (a & UINT64_C(0x0007FFFFFFFFFFFF));
uint64_t a = float64_val(a_);
if (snan_bit_is_one(status)) {
return ((a << 1) >= 0xFFF0000000000000ULL);
} else {
return (((a >> 51) & 0xFFF) == 0xFFE)
&& (a & UINT64_C(0x0007FFFFFFFFFFFF));
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -757,7 +807,7 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
aIsLargerSignificand = (av < bv) ? 1 : 0;
}
if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
if (is_snan(b_cls)) {
return float64_silence_nan(b, status);
}
@ -778,21 +828,21 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
int floatx80_is_quiet_nan(floatx80 a, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return floatx80_is_any_nan(a);
#else
if (snan_bit_is_one(status)) {
uint64_t aLow;
aLow = a.low & ~0x4000000000000000ULL;
return ((a.high & 0x7FFF) == 0x7FFF)
&& (aLow << 1)
&& (a.low == aLow);
if (no_signaling_nans(status)) {
return floatx80_is_any_nan(a);
} else {
return ((a.high & 0x7FFF) == 0x7FFF)
&& (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
if (snan_bit_is_one(status)) {
uint64_t aLow;
aLow = a.low & ~0x4000000000000000ULL;
return ((a.high & 0x7FFF) == 0x7FFF)
&& (aLow << 1)
&& (a.low == aLow);
} else {
return ((a.high & 0x7FFF) == 0x7FFF)
&& (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -803,21 +853,21 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status)
int floatx80_is_signaling_nan(floatx80 a, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return 0;
#else
if (snan_bit_is_one(status)) {
return ((a.high & 0x7FFF) == 0x7FFF)
&& ((a.low << 1) >= 0x8000000000000000ULL);
if (no_signaling_nans(status)) {
return 0;
} else {
uint64_t aLow;
if (snan_bit_is_one(status)) {
return ((a.high & 0x7FFF) == 0x7FFF)
&& ((a.low << 1) >= 0x8000000000000000ULL);
} else {
uint64_t aLow;
aLow = a.low & ~UINT64_C(0x4000000000000000);
return ((a.high & 0x7FFF) == 0x7FFF)
&& (uint64_t)(aLow << 1)
&& (a.low == aLow);
aLow = a.low & ~UINT64_C(0x4000000000000000);
return ((a.high & 0x7FFF) == 0x7FFF)
&& (uint64_t)(aLow << 1)
&& (a.low == aLow);
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -921,7 +971,7 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
}
if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
if (is_snan(b_cls)) {
return floatx80_silence_nan(b, status);
}
@ -941,17 +991,17 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
bool float128_is_quiet_nan(float128 a, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return float128_is_any_nan(a);
#else
if (snan_bit_is_one(status)) {
return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
&& (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
if (no_signaling_nans(status)) {
return float128_is_any_nan(a);
} else {
return ((a.high << 1) >= 0xFFFF000000000000ULL)
&& (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
if (snan_bit_is_one(status)) {
return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
&& (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
} else {
return ((a.high << 1) >= 0xFFFF000000000000ULL)
&& (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -961,17 +1011,17 @@ bool float128_is_quiet_nan(float128 a, float_status *status)
bool float128_is_signaling_nan(float128 a, float_status *status)
{
#ifdef NO_SIGNALING_NANS
return 0;
#else
if (snan_bit_is_one(status)) {
return ((a.high << 1) >= 0xFFFF000000000000ULL)
&& (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
if (no_signaling_nans(status)) {
return 0;
} else {
return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
&& (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
if (snan_bit_is_one(status)) {
return ((a.high << 1) >= 0xFFFF000000000000ULL)
&& (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
} else {
return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
&& (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -981,16 +1031,16 @@ bool float128_is_signaling_nan(float128 a, float_status *status)
float128 float128_silence_nan(float128 a, float_status *status)
{
#ifdef NO_SIGNALING_NANS
g_assert_not_reached();
#else
if (snan_bit_is_one(status)) {
return float128_default_nan(status);
if (no_signaling_nans(status)) {
g_assert_not_reached();
} else {
a.high |= UINT64_C(0x0000800000000000);
return a;
if (snan_bit_is_one(status)) {
return float128_default_nan(status);
} else {
a.high |= UINT64_C(0x0000800000000000);
return a;
}
}
#endif
}
/*----------------------------------------------------------------------------
@ -1069,7 +1119,7 @@ static float128 propagateFloat128NaN(float128 a, float128 b,
aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
}
if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) {
if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
if (is_snan(b_cls)) {
return float128_silence_nan(b, status);
}

2
fpu/softfloat.c
View File

@ -881,7 +881,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s)
} else {
if (pickNaN(a.cls, b.cls,
a.frac > b.frac ||
(a.frac == b.frac && a.sign < b.sign))) {
(a.frac == b.frac && a.sign < b.sign), s)) {
a = b;
}
if (is_snan(a.cls)) {

6
hw/xtensa/pic_cpu.c
View File

@ -35,9 +35,13 @@ void check_interrupts(CPUXtensaState *env)
{
CPUState *cs = env_cpu(env);
int minlevel = xtensa_get_cintlevel(env);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
uint32_t int_set_enabled = env->sregs[INTSET] &
(env->sregs[INTENABLE] | env->config->inttype_mask[INTTYPE_NMI]);
int level;
if (minlevel >= env->config->nmi_level) {
minlevel = env->config->nmi_level - 1;
}
for (level = env->config->nlevel; level > minlevel; --level) {
if (env->config->level_mask[level] & int_set_enabled) {
env->pending_irq_level = level;

10
include/fpu/softfloat-helpers.h
View File

@ -95,6 +95,16 @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
status->snan_bit_is_one = val;
}
static inline void set_use_first_nan(bool val, float_status *status)
{
status->use_first_nan = val;
}
static inline void set_no_signaling_nans(bool val, float_status *status)
{
status->no_signaling_nans = val;
}
static inline bool get_float_detect_tininess(float_status *status)
{
return status->tininess_before_rounding;

8
include/fpu/softfloat-types.h
View File

@ -165,8 +165,14 @@ typedef struct float_status {
/* should denormalised inputs go to zero and set the input_denormal flag? */
bool flush_inputs_to_zero;
bool default_nan_mode;
/* not always used -- see snan_bit_is_one() in softfloat-specialize.h */
/*
* The flags below are not used on all specializations and may
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
* softfloat-specialize.inc.c)
*/
bool snan_bit_is_one;
bool use_first_nan;
bool no_signaling_nans;
} float_status;
#endif /* SOFTFLOAT_TYPES_H */

58
target/xtensa/core-de233_fpu.c Normal file
View File

@ -0,0 +1,58 @@
/*
* Copyright (c) 2020, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/gdbstub.h"
#include "qemu-common.h"
#include "qemu/host-utils.h"
#include "core-de233_fpu/core-isa.h"
#include "core-de233_fpu/core-matmap.h"
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_de233_fpu
#include "core-de233_fpu/xtensa-modules.c.inc"
static XtensaConfig de233_fpu __attribute__((unused)) = {
.name = "de233_fpu",
.gdb_regmap = {
.reg = {
#include "core-de233_fpu/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
.clock_freq_khz = 40000,
.opcode_translators = (const XtensaOpcodeTranslators *[]){
&xtensa_core_opcodes,
&xtensa_fpu_opcodes,
NULL,
},
DEFAULT_SECTIONS
};
REGISTER_CORE(de233_fpu)

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/*
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
* processor CORE configuration
*
* See <xtensa/config/core.h>, which includes this file, for more details.
*/
/* Xtensa processor core configuration information.
Copyright (c) 1999-2020 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CORE_CONFIGURATION_H_
#define XTENSA_CORE_CONFIGURATION_H_
//depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko)
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
#define XCHAL_HAVE_LX 1 /* LX core */
#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */
#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
#define XCHAL_HAVE_FP 1 /* single prec floating point */
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
#define XCHAL_HAVE_DFP 1 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_DIV 1 /* DFP with DIV instructions */
#define XCHAL_HAVE_DFP_RECIP 1 /* DFP with RECIP instructions*/
#define XCHAL_HAVE_DFP_SQRT 1 /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT 1 /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 1 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */
#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */
#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */
#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */
#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */
#define XCHAL_HAVE_PDX 0 /* PDX-LX */
#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */
#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */
#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */
#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
#define XCHAL_HAVE_BALL 0
#define XCHAL_HAVE_BALLAP 0
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/
#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/
#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */
#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */
#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6 or Q7 */
#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */
#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */
#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */
#define XCHAL_HAVE_VISIONC 0 /* Vision C */
#define XCHAL_HAVE_XNNE 0 /* XNNE */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
(1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
#define XCHAL_UNIFIED_LOADSTORE 0
#define XCHAL_SW_VERSION 1403000 /* sw version of this header */
#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */
#define XCHAL_SW_VERSION_MINOR 3 /* minor ver# of sw */
#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */
#define XCHAL_SW_MINOR_VERSION 1403000 /* with zeroed micro */
#define XCHAL_SW_MICRO_VERSION 1403000
#define XCHAL_CORE_ID "DE_233L_FPU" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x000872E0 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC1039286 /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x28C872E0 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX7.1.3" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */
#define XCHAL_HW_VERSION 281030 /* major*100+(major<2810 ? minor : minor*10+micro) */
#define XCHAL_HW_REL_LX7 1
#define XCHAL_HW_REL_LX7_1 1
#define XCHAL_HW_REL_LX7_1_3 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 281030 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 281030 /* latest targeted hw */
/* Config is enabled for functional safety: */
#define XCHAL_HAVE_FUNC_SAFETY 0
#define XCHAL_HAVE_APB 0
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
#define XCHAL_ICACHE_SIZE_LOG2 14
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE_LOG2 14
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
#define XCHAL_HAVE_CME_DOWNGRADES 0
#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
#define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */
#define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */
#define XCHAL_L1SCACHE_SIZE 0
#define XCHAL_L1SCACHE_SIZE_LOG2 0
#define XCHAL_L1SCACHE_WAYS 1
#define XCHAL_L1SCACHE_WAYS_LOG2 0
#define XCHAL_L1SCACHE_ACCESS_SIZE 0
#define XCHAL_L1SCACHE_BANKS 1
#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */
/* Number of cores in cluster */
#if XCHAL_HAVE_L2
#define XCHAL_NUM_CORES_IN_CLUSTER XCHAL_L2CC_NUM_CORES_LOG2
#else
#define XCHAL_NUM_CORES_IN_CLUSTER 0
#endif
/* PRID_ID macros are for internal use only ... subject to removal */
#define PRID_ID_SHIFT 0
#define PRID_ID_BITS 4
#define PRID_ID_MASK 0x0000000F
/* This one is a form of caching, though not architecturally visible: */
#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
#define XCHAL_HAVE_AXI 0 /* AXI bus */
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 7
#define XCHAL_DCACHE_SETWIDTH 7
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 4
#define XCHAL_ICACHE_WAYS_LOG2 2
#define XCHAL_DCACHE_WAYS 4
#define XCHAL_DCACHE_WAYS_LOG2 2
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 1
#define XCHAL_DCACHE_LINE_LOCKABLE 1
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
#define XCHAL_ICACHE_ECC_WIDTH 4
#define XCHAL_DCACHE_ECC_WIDTH 1
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 4
#define XCHAL_DCACHE_ACCESS_SIZE 8
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
/* The number of Cache lines associated with a single cache tag */
#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */
#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */
#define XCHAL_HAVE_IDMA 0
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
(not including level zero) */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x001F80FF
#define XCHAL_INTLEVEL2_MASK 0x00000100
#define XCHAL_INTLEVEL3_MASK 0x00200E00
#define XCHAL_INTLEVEL4_MASK 0x00001000
#define XCHAL_INTLEVEL5_MASK 0x00002000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00004000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 2
#define XCHAL_INT9_LEVEL 3
#define XCHAL_INT10_LEVEL 3
#define XCHAL_INT11_LEVEL 3
#define XCHAL_INT12_LEVEL 4
#define XCHAL_INT13_LEVEL 5
#define XCHAL_INT14_LEVEL 7
#define XCHAL_INT15_LEVEL 1
#define XCHAL_INT16_LEVEL 1
#define XCHAL_INT17_LEVEL 1
#define XCHAL_INT18_LEVEL 1
#define XCHAL_INT19_LEVEL 1
#define XCHAL_INT20_LEVEL 1
#define XCHAL_INT21_LEVEL 3
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
EXCSAVE/EPS/EPC_n, RFI n) */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000
#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000
#define XCHAL_INTTYPE_MASK_TRAX 0x00000000
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000
#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000
#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL2_NUM 8
#define XCHAL_INTLEVEL4_NUM 12
#define XCHAL_INTLEVEL5_NUM 13
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 3.) */
/*
* External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
#define XCHAL_HAVE_ISB 0 /* No ISB */
#define XCHAL_ISB_VADDR 0 /* N/A */
#define XCHAL_HAVE_ITB 0 /* No ITB */
#define XCHAL_ITB_VADDR 0 /* N/A */
#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */
#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */
#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (until T1050)
2 == XEA2 (T1040 onwards)
3 == XEA3 (LX8/NX/SX onwards)
0 == XEAX (extern) or TX */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */
#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x00002000
#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR
#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR
#define XCHAL_USER_VECOFS 0x00000340
#define XCHAL_USER_VECTOR_VADDR 0x00002340
#define XCHAL_USER_VECTOR_PADDR 0x00002340
#define XCHAL_KERNEL_VECOFS 0x00000300
#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x000002C0
#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG MODULE
----------------------------------------------------------------------*/
/* Misc */
#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
/* On-Chip Debug (OCD) */
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
/* TRAX (in core) */
#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 5 are set, it's a custom TLB configuration. */
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
/*----------------------------------------------------------------------
MPU
----------------------------------------------------------------------*/
#define XCHAL_HAVE_MPU 0
#define XCHAL_MPU_ENTRIES 0
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
#define XCHAL_MPU_ALIGN_BITS 0
#define XCHAL_MPU_ALIGN 0
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* XTENSA_CORE_CONFIGURATION_H_ */

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/*
* xtensa/config/core-matmap.h -- Memory access and translation mapping
* parameters (CHAL) of the Xtensa processor core configuration.
*
* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
* this file) for more details.
*
* In the Xtensa processor products released to date, all parameters
* defined in this file are derivable (at least in theory) from
* information contained in the core-isa.h header file.
* In particular, the following core configuration parameters are relevant:
* XCHAL_HAVE_CACHEATTR
* XCHAL_HAVE_MIMIC_CACHEATTR
* XCHAL_HAVE_XLT_CACHEATTR
* XCHAL_HAVE_PTP_MMU
* XCHAL_ITLB_ARF_ENTRIES_LOG2
* XCHAL_DTLB_ARF_ENTRIES_LOG2
* XCHAL_DCACHE_IS_WRITEBACK
* XCHAL_ICACHE_SIZE (presence of I-cache)
* XCHAL_DCACHE_SIZE (presence of D-cache)
* XCHAL_HW_VERSION_MAJOR
* XCHAL_HW_VERSION_MINOR
*/
/* Copyright (c) 1999-2020 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
#define XTENSA_CONFIG_CORE_MATMAP_H
/*----------------------------------------------------------------------
CACHE (MEMORY ACCESS) ATTRIBUTES
----------------------------------------------------------------------*/
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION
#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION
#define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITEBACK XCHAL_SEP \
XTHAL_SAM_WRITEBACK XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION
#define XCHAL_CA_R (0xC0 | 0x40000000)
#define XCHAL_CA_RX (0xD0 | 0x40000000)
#define XCHAL_CA_RW (0xE0 | 0x40000000)
#define XCHAL_CA_RWX (0xF0 | 0x40000000)
/*
* Specific encoded cache attribute values of general interest.
* If a specific cache mode is not available, the closest available
* one is returned instead (eg. writethru instead of writeback,
* bypass instead of writethru).
*/
#define XCHAL_CA_BYPASS 3 /* cache disabled (bypassed) mode */
#define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
#define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */
#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
#define XCHAL_CA_WRITEBACK_NOALLOC 7 /* cache enabled (write-back no-allocate) mode */
#define XCHAL_CA_BYPASS_RX 1 /* cache disabled (bypassed) mode (no write) */
#define XCHAL_CA_WRITETHRU_RX 9 /* cache enabled (write-through) mode (no write) */
#define XCHAL_CA_WRITEBACK_RX 5 /* cache enabled (write-back) mode (no write) */
#define XCHAL_CA_WRITEBACK_NOALLOC_RX 5 /* cache enabled (write-back no-allocate) mode (no write) */
#define XCHAL_CA_BYPASS_RW 2 /* cache disabled (bypassed) mode (no exec) */
#define XCHAL_CA_WRITETHRU_RW 10 /* cache enabled (write-through) mode (no exec) */
#define XCHAL_CA_WRITEBACK_RW 6 /* cache enabled (write-back) mode (no exec) */
#define XCHAL_CA_WRITEBACK_NOALLOC_RW 6 /* cache enabled (write-back no-allocate) mode (no exec) */
#define XCHAL_CA_BYPASS_R 0 /* cache disabled (bypassed) mode (no exec, no write) */
#define XCHAL_CA_WRITETHRU_R 8 /* cache enabled (write-through) mode (no exec, no write) */
#define XCHAL_CA_WRITEBACK_R 4 /* cache enabled (write-back) mode (no exec, no write) */
#define XCHAL_CA_WRITEBACK_NOALLOC_R 4 /* cache enabled (write-back no-allocate) mode (no exec, no write) */
#define XCHAL_CA_ILLEGAL 12 /* no access allowed (all cause exceptions) mode */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/*
* General notes on MMU parameters.
*
* Terminology:
* ASID = address-space ID (acts as an "extension" of virtual addresses)
* VPN = virtual page number
* PPN = physical page number
* CA = encoded cache attribute (access modes)
* TLB = translation look-aside buffer (term is stretched somewhat here)
* I = instruction (fetch accesses)
* D = data (load and store accesses)
* way = each TLB (ITLB and DTLB) consists of a number of "ways"
* that simultaneously match the virtual address of an access;
* a TLB successfully translates a virtual address if exactly
* one way matches the vaddr; if none match, it is a miss;
* if multiple match, one gets a "multihit" exception;
* each way can be independently configured in terms of number of
* entries, page sizes, which fields are writable or constant, etc.
* set = group of contiguous ways with exactly identical parameters
* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
* from the page table and storing it in one of the auto-refill ways;
* if this PTE load also misses, a miss exception is posted for s/w.
* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
* page arbitrarily under program control; it has a single entry,
* is non-auto-refill (some other way(s) must be auto-refill),
* all its fields (VPN, PPN, ASID, CA) are all writable, and it
* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
* restriction is that this be the only page size it supports).
*
* TLB way entries are virtually indexed.
* TLB ways that support multiple page sizes:
* - must have all writable VPN and PPN fields;
* - can only use one page size at any given time (eg. setup at startup),
* selected by the respective ITLBCFG or DTLBCFG special register,
* whose bits n*4+3 .. n*4 index the list of page sizes for way n
* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
* this list may be sparse for auto-refill ways because auto-refill
* ways have independent lists of supported page sizes sharing a
* common encoding with PTE entries; the encoding is the index into
* this list; unsupported sizes for a given way are zero in the list;
* selecting unsupported sizes results in undefine hardware behaviour;
* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
*/
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
#define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
/*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
#define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
#define XCHAL_ITLB_SETS 7 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_ITLB_WAY0_SET 0
#define XCHAL_ITLB_WAY1_SET 1
#define XCHAL_ITLB_WAY2_SET 2
#define XCHAL_ITLB_WAY3_SET 3
#define XCHAL_ITLB_WAY4_SET 4
#define XCHAL_ITLB_WAY5_SET 5
#define XCHAL_ITLB_WAY6_SET 6
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_ITLB_ARF_SETS 4 /* number of auto-refill sets */
#define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
#define XCHAL_ITLB_ARF_SET1 1 /* index of n'th auto-refill set */
#define XCHAL_ITLB_ARF_SET2 2 /* index of n'th auto-refill set */
#define XCHAL_ITLB_ARF_SET3 3 /* index of n'th auto-refill set */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* ITLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* ITLB way set 1 (group of ways 1 thru 1): */
#define XCHAL_ITLB_SET1_WAY 1 /* index of first way in this way set */
#define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* ITLB way set 2 (group of ways 2 thru 2): */
#define XCHAL_ITLB_SET2_WAY 2 /* index of first way in this way set */
#define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* ITLB way set 3 (group of ways 3 thru 3): */
#define XCHAL_ITLB_SET3_WAY 3 /* index of first way in this way set */
#define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* ITLB way set 4 (group of ways 4 thru 4): */
#define XCHAL_ITLB_SET4_WAY 4 /* index of first way in this way set */
#define XCHAL_ITLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* ITLB way set 5 (group of ways 5 thru 5): */
#define XCHAL_ITLB_SET5_WAY 5 /* index of first way in this way set */
#define XCHAL_ITLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Reset ASID values for each entry of ITLB way set 5 (because SET5_ASID_RESET is non-zero): */
#define XCHAL_ITLB_SET5_E0_ASID_RESET 0x00
#define XCHAL_ITLB_SET5_E1_ASID_RESET 0x00
#define XCHAL_ITLB_SET5_E2_ASID_RESET 0x00
#define XCHAL_ITLB_SET5_E3_ASID_RESET 0x00
/* Reset VPN values for each entry of ITLB way set 5 (because SET5_VPN_RESET is non-zero): */
#define XCHAL_ITLB_SET5_E0_VPN_RESET 0x00000000
#define XCHAL_ITLB_SET5_E1_VPN_RESET 0x00000000
#define XCHAL_ITLB_SET5_E2_VPN_RESET 0x00000000
#define XCHAL_ITLB_SET5_E3_VPN_RESET 0x00000000
/* Reset PPN values for each entry of ITLB way set 5 (because SET5_PPN_RESET is non-zero): */
#define XCHAL_ITLB_SET5_E0_PPN_RESET 0x00000000
#define XCHAL_ITLB_SET5_E1_PPN_RESET 0x00000000
#define XCHAL_ITLB_SET5_E2_PPN_RESET 0x00000000
#define XCHAL_ITLB_SET5_E3_PPN_RESET 0x00000000
/* ITLB way set 6 (group of ways 6 thru 6): */
#define XCHAL_ITLB_SET6_WAY 6 /* index of first way in this way set */
#define XCHAL_ITLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Reset ASID values for each entry of ITLB way set 6 (because SET6_ASID_RESET is non-zero): */
#define XCHAL_ITLB_SET6_E0_ASID_RESET 0x01
#define XCHAL_ITLB_SET6_E1_ASID_RESET 0x01
#define XCHAL_ITLB_SET6_E2_ASID_RESET 0x01
#define XCHAL_ITLB_SET6_E3_ASID_RESET 0x01
#define XCHAL_ITLB_SET6_E4_ASID_RESET 0x01
#define XCHAL_ITLB_SET6_E5_ASID_RESET 0x01
#define XCHAL_ITLB_SET6_E6_ASID_RESET 0x01
#define XCHAL_ITLB_SET6_E7_ASID_RESET 0x01
/* Reset VPN values for each entry of ITLB way set 6 (because SET6_VPN_RESET is non-zero): */
#define XCHAL_ITLB_SET6_E0_VPN_RESET 0x00000000
#define XCHAL_ITLB_SET6_E1_VPN_RESET 0x20000000
#define XCHAL_ITLB_SET6_E2_VPN_RESET 0x40000000
#define XCHAL_ITLB_SET6_E3_VPN_RESET 0x60000000
#define XCHAL_ITLB_SET6_E4_VPN_RESET 0x80000000
#define XCHAL_ITLB_SET6_E5_VPN_RESET 0xA0000000
#define XCHAL_ITLB_SET6_E6_VPN_RESET 0xC0000000
#define XCHAL_ITLB_SET6_E7_VPN_RESET 0xE0000000
/* Reset PPN values for each entry of ITLB way set 6 (because SET6_PPN_RESET is non-zero): */
#define XCHAL_ITLB_SET6_E0_PPN_RESET 0x00000000
#define XCHAL_ITLB_SET6_E1_PPN_RESET 0x20000000
#define XCHAL_ITLB_SET6_E2_PPN_RESET 0x40000000
#define XCHAL_ITLB_SET6_E3_PPN_RESET 0x60000000
#define XCHAL_ITLB_SET6_E4_PPN_RESET 0x80000000
#define XCHAL_ITLB_SET6_E5_PPN_RESET 0xA0000000
#define XCHAL_ITLB_SET6_E6_PPN_RESET 0xC0000000
#define XCHAL_ITLB_SET6_E7_PPN_RESET 0xE0000000
/* Reset CA values for each entry of ITLB way set 6 (because SET6_CA_RESET is non-zero): */
#define XCHAL_ITLB_SET6_E0_CA_RESET 0x03
#define XCHAL_ITLB_SET6_E1_CA_RESET 0x03
#define XCHAL_ITLB_SET6_E2_CA_RESET 0x03
#define XCHAL_ITLB_SET6_E3_CA_RESET 0x03
#define XCHAL_ITLB_SET6_E4_CA_RESET 0x03
#define XCHAL_ITLB_SET6_E5_CA_RESET 0x03
#define XCHAL_ITLB_SET6_E6_CA_RESET 0x03
#define XCHAL_ITLB_SET6_E7_CA_RESET 0x03
/*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
#define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
#define XCHAL_DTLB_SETS 10 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_DTLB_WAY0_SET 0
#define XCHAL_DTLB_WAY1_SET 1
#define XCHAL_DTLB_WAY2_SET 2
#define XCHAL_DTLB_WAY3_SET 3
#define XCHAL_DTLB_WAY4_SET 4
#define XCHAL_DTLB_WAY5_SET 5
#define XCHAL_DTLB_WAY6_SET 6
#define XCHAL_DTLB_WAY7_SET 7
#define XCHAL_DTLB_WAY8_SET 8
#define XCHAL_DTLB_WAY9_SET 9
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_DTLB_ARF_SETS 4 /* number of auto-refill sets */
#define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
#define XCHAL_DTLB_ARF_SET1 1 /* index of n'th auto-refill set */
#define XCHAL_DTLB_ARF_SET2 2 /* index of n'th auto-refill set */
#define XCHAL_DTLB_ARF_SET3 3 /* index of n'th auto-refill set */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_DTLB_MINWIRED_SETS 3 /* number of "min-wired" sets */
#define XCHAL_DTLB_MINWIRED_SET0 7 /* index of n'th "min-wired" set */
#define XCHAL_DTLB_MINWIRED_SET1 8 /* index of n'th "min-wired" set */
#define XCHAL_DTLB_MINWIRED_SET2 9 /* index of n'th "min-wired" set */
/* DTLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* DTLB way set 1 (group of ways 1 thru 1): */
#define XCHAL_DTLB_SET1_WAY 1 /* index of first way in this way set */
#define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* DTLB way set 2 (group of ways 2 thru 2): */
#define XCHAL_DTLB_SET2_WAY 2 /* index of first way in this way set */
#define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* DTLB way set 3 (group of ways 3 thru 3): */
#define XCHAL_DTLB_SET3_WAY 3 /* index of first way in this way set */
#define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* DTLB way set 4 (group of ways 4 thru 4): */
#define XCHAL_DTLB_SET4_WAY 4 /* index of first way in this way set */
#define XCHAL_DTLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* DTLB way set 5 (group of ways 5 thru 5): */
#define XCHAL_DTLB_SET5_WAY 5 /* index of first way in this way set */
#define XCHAL_DTLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Reset ASID values for each entry of DTLB way set 5 (because SET5_ASID_RESET is non-zero): */
#define XCHAL_DTLB_SET5_E0_ASID_RESET 0x00
#define XCHAL_DTLB_SET5_E1_ASID_RESET 0x00
#define XCHAL_DTLB_SET5_E2_ASID_RESET 0x00
#define XCHAL_DTLB_SET5_E3_ASID_RESET 0x00
/* Reset VPN values for each entry of DTLB way set 5 (because SET5_VPN_RESET is non-zero): */
#define XCHAL_DTLB_SET5_E0_VPN_RESET 0x00000000
#define XCHAL_DTLB_SET5_E1_VPN_RESET 0x00000000
#define XCHAL_DTLB_SET5_E2_VPN_RESET 0x00000000
#define XCHAL_DTLB_SET5_E3_VPN_RESET 0x00000000
/* Reset PPN values for each entry of DTLB way set 5 (because SET5_PPN_RESET is non-zero): */
#define XCHAL_DTLB_SET5_E0_PPN_RESET 0x00000000
#define XCHAL_DTLB_SET5_E1_PPN_RESET 0x00000000
#define XCHAL_DTLB_SET5_E2_PPN_RESET 0x00000000
#define XCHAL_DTLB_SET5_E3_PPN_RESET 0x00000000
/* DTLB way set 6 (group of ways 6 thru 6): */
#define XCHAL_DTLB_SET6_WAY 6 /* index of first way in this way set */
#define XCHAL_DTLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Reset ASID values for each entry of DTLB way set 6 (because SET6_ASID_RESET is non-zero): */
#define XCHAL_DTLB_SET6_E0_ASID_RESET 0x01
#define XCHAL_DTLB_SET6_E1_ASID_RESET 0x01
#define XCHAL_DTLB_SET6_E2_ASID_RESET 0x01
#define XCHAL_DTLB_SET6_E3_ASID_RESET 0x01
#define XCHAL_DTLB_SET6_E4_ASID_RESET 0x01
#define XCHAL_DTLB_SET6_E5_ASID_RESET 0x01
#define XCHAL_DTLB_SET6_E6_ASID_RESET 0x01
#define XCHAL_DTLB_SET6_E7_ASID_RESET 0x01
/* Reset VPN values for each entry of DTLB way set 6 (because SET6_VPN_RESET is non-zero): */
#define XCHAL_DTLB_SET6_E0_VPN_RESET 0x00000000
#define XCHAL_DTLB_SET6_E1_VPN_RESET 0x20000000
#define XCHAL_DTLB_SET6_E2_VPN_RESET 0x40000000
#define XCHAL_DTLB_SET6_E3_VPN_RESET 0x60000000
#define XCHAL_DTLB_SET6_E4_VPN_RESET 0x80000000
#define XCHAL_DTLB_SET6_E5_VPN_RESET 0xA0000000
#define XCHAL_DTLB_SET6_E6_VPN_RESET 0xC0000000
#define XCHAL_DTLB_SET6_E7_VPN_RESET 0xE0000000
/* Reset PPN values for each entry of DTLB way set 6 (because SET6_PPN_RESET is non-zero): */
#define XCHAL_DTLB_SET6_E0_PPN_RESET 0x00000000
#define XCHAL_DTLB_SET6_E1_PPN_RESET 0x20000000
#define XCHAL_DTLB_SET6_E2_PPN_RESET 0x40000000
#define XCHAL_DTLB_SET6_E3_PPN_RESET 0x60000000
#define XCHAL_DTLB_SET6_E4_PPN_RESET 0x80000000
#define XCHAL_DTLB_SET6_E5_PPN_RESET 0xA0000000
#define XCHAL_DTLB_SET6_E6_PPN_RESET 0xC0000000
#define XCHAL_DTLB_SET6_E7_PPN_RESET 0xE0000000
/* Reset CA values for each entry of DTLB way set 6 (because SET6_CA_RESET is non-zero): */
#define XCHAL_DTLB_SET6_E0_CA_RESET 0x03
#define XCHAL_DTLB_SET6_E1_CA_RESET 0x03
#define XCHAL_DTLB_SET6_E2_CA_RESET 0x03
#define XCHAL_DTLB_SET6_E3_CA_RESET 0x03
#define XCHAL_DTLB_SET6_E4_CA_RESET 0x03
#define XCHAL_DTLB_SET6_E5_CA_RESET 0x03
#define XCHAL_DTLB_SET6_E6_CA_RESET 0x03
#define XCHAL_DTLB_SET6_E7_CA_RESET 0x03
/* DTLB way set 7 (group of ways 7 thru 7): */
#define XCHAL_DTLB_SET7_WAY 7 /* index of first way in this way set */
#define XCHAL_DTLB_SET7_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET7_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET7_ENTRIES 1 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET7_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET7_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET7_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET7_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET7_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET7_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET7_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET7_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET7_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET7_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET7_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET7_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET7_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET7_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* DTLB way set 8 (group of ways 8 thru 8): */
#define XCHAL_DTLB_SET8_WAY 8 /* index of first way in this way set */
#define XCHAL_DTLB_SET8_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET8_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET8_ENTRIES 1 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET8_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET8_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET8_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET8_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET8_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET8_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET8_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET8_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET8_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET8_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET8_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET8_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET8_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET8_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* DTLB way set 9 (group of ways 9 thru 9): */
#define XCHAL_DTLB_SET9_WAY 9 /* index of first way in this way set */
#define XCHAL_DTLB_SET9_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET9_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET9_ENTRIES 1 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET9_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET9_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET9_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET9_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET9_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET9_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET9_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET9_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET9_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET9_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET9_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET9_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET9_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET9_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/

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target/xtensa/core-de233_fpu/gdb-config.c.inc Normal file
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/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
Copyright (c) 2003-2020 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
XTREG( 42,168,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
XTREG( 43,172,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
XTREG( 45,180,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
XTREG( 46,184, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
XTREG( 47,188,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
XTREG( 48,192,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
XTREG( 49,196,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
XTREG( 50,200,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
XTREG( 51,204,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
XTREG( 52,208,64, 8, 8,0x0030,0x0006, 0, 4,0x0401,f0,
"03:03:54:00","03:03:14:00",0,0,0,0)
XTREG( 53,216,64, 8, 8,0x0031,0x0006, 0, 4,0x0401,f1,
"03:13:54:00","03:13:14:00",0,0,0,0)
XTREG( 54,224,64, 8, 8,0x0032,0x0006, 0, 4,0x0401,f2,
"03:23:54:00","03:23:14:00",0,0,0,0)
XTREG( 55,232,64, 8, 8,0x0033,0x0006, 0, 4,0x0401,f3,
"03:33:54:00","03:33:14:00",0,0,0,0)
XTREG( 56,240,64, 8, 8,0x0034,0x0006, 0, 4,0x0401,f4,
"03:43:54:00","03:43:14:00",0,0,0,0)
XTREG( 57,248,64, 8, 8,0x0035,0x0006, 0, 4,0x0401,f5,
"03:53:54:00","03:53:14:00",0,0,0,0)
XTREG( 58,256,64, 8, 8,0x0036,0x0006, 0, 4,0x0401,f6,
"03:63:54:00","03:63:14:00",0,0,0,0)
XTREG( 59,264,64, 8, 8,0x0037,0x0006, 0, 4,0x0401,f7,
"03:73:54:00","03:73:14:00",0,0,0,0)
XTREG( 60,272,64, 8, 8,0x0038,0x0006, 0, 4,0x0401,f8,
"03:83:54:00","03:83:14:00",0,0,0,0)
XTREG( 61,280,64, 8, 8,0x0039,0x0006, 0, 4,0x0401,f9,
"03:93:54:00","03:93:14:00",0,0,0,0)
XTREG( 62,288,64, 8, 8,0x003a,0x0006, 0, 4,0x0401,f10,
"03:a3:54:00","03:a3:14:00",0,0,0,0)
XTREG( 63,296,64, 8, 8,0x003b,0x0006, 0, 4,0x0401,f11,
"03:b3:54:00","03:b3:14:00",0,0,0,0)
XTREG( 64,304,64, 8, 8,0x003c,0x0006, 0, 4,0x0401,f12,
"03:c3:54:00","03:c3:14:00",0,0,0,0)
XTREG( 65,312,64, 8, 8,0x003d,0x0006, 0, 4,0x0401,f13,
"03:d3:54:00","03:d3:14:00",0,0,0,0)
XTREG( 66,320,64, 8, 8,0x003e,0x0006, 0, 4,0x0401,f14,
"03:e3:54:00","03:e3:14:00",0,0,0,0)
XTREG( 67,328,64, 8, 8,0x003f,0x0006, 0, 4,0x0401,f15,
"03:f3:54:00","03:f3:14:00",0,0,0,0)
XTREG( 68,336,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0)
XTREG( 69,340,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0)
XTREG( 70,344,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
XTREG( 71,348,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
XTREG( 72,352,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
XTREG( 73,356,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
XTREG( 74,360,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
XTREG( 75,364,16, 4, 4,0x025f,0x0007,-2, 2,0x1000,eraccess, 0,0,0,0,0,0)
XTREG( 76,368, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
XTREG( 77,372, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
XTREG( 78,376,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
XTREG( 79,380,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
XTREG( 80,384,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
XTREG( 81,388,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
XTREG( 82,392,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
XTREG( 83,396,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
XTREG( 84,400,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
XTREG( 85,404,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
XTREG( 86,408,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
XTREG( 87,412,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
XTREG( 88,416,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
XTREG( 89,420,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
XTREG( 90,424,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
XTREG( 91,428,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
XTREG( 92,432,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
XTREG( 93,436,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
XTREG( 94,440,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
XTREG( 95,444,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
XTREG( 96,448,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
XTREG( 97,452,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
XTREG( 98,456,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
XTREG( 99,460,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
XTREG(100,464,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
XTREG(101,468,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
XTREG(102,472,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
XTREG(103,476,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
XTREG(104,480,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
XTREG(105,484,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
XTREG(106,488, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
XTREG(107,492,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
XTREG(108,496,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
XTREG(109,500,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
XTREG(110,504,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
XTREG(111,508,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
XTREG(112,512, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
XTREG(113,516,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
XTREG(114,520,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
XTREG(115,524,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
XTREG(116,528,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
XTREG(117,532, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
XTREG(118,536,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
XTREG(119,540,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
XTREG(120,544,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
XTREG(121,548,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
XTREG(122,552,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
XTREG(123,556,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
XTREG(124,560,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0)
XTREG(125,564,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0)
XTREG(126,568,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0)
XTREG(127,572,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0)
XTREG(128,576,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0)
XTREG(129,580,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0)
XTREG(130,584,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0)
XTREG(131,588,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0)
XTREG(132,592,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0)
XTREG(133,596,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0)
XTREG(134,600,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0)
XTREG(135,604,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0)
XTREG(136,608,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0)
XTREG(137,612,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0)
XTREG(138,616,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0)
XTREG(139,620,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0)
XTREG(140,624, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
0,0,&xtensa_mask0,0,0,0)
XTREG(141,625, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
0,0,&xtensa_mask1,0,0,0)
XTREG(142,626, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
0,0,&xtensa_mask2,0,0,0)
XTREG(143,627, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
0,0,&xtensa_mask3,0,0,0)
XTREG(144,628, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
0,0,&xtensa_mask4,0,0,0)
XTREG(145,629, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
0,0,&xtensa_mask5,0,0,0)
XTREG(146,630, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
0,0,&xtensa_mask6,0,0,0)
XTREG(147,631, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
0,0,&xtensa_mask7,0,0,0)
XTREG(148,632, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
0,0,&xtensa_mask8,0,0,0)
XTREG(149,633, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
0,0,&xtensa_mask9,0,0,0)
XTREG(150,634, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
0,0,&xtensa_mask10,0,0,0)
XTREG(151,635, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
0,0,&xtensa_mask11,0,0,0)
XTREG(152,636, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
0,0,&xtensa_mask12,0,0,0)
XTREG(153,637, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
0,0,&xtensa_mask13,0,0,0)
XTREG(154,638, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
0,0,&xtensa_mask14,0,0,0)
XTREG(155,639, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
0,0,&xtensa_mask15,0,0,0)
XTREG(156,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
0,0,&xtensa_mask16,0,0,0)
XTREG(157,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
0,0,&xtensa_mask17,0,0,0)
XTREG(158,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
0,0,&xtensa_mask18,0,0,0)
XTREG(159,652, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
0,0,&xtensa_mask19,0,0,0)
XTREG(160,656, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
0,0,&xtensa_mask20,0,0,0)
XTREG(161,660, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
0,0,&xtensa_mask21,0,0,0)
XTREG(162,664, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
0,0,&xtensa_mask22,0,0,0)
XTREG(163,668,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc,
0,0,&xtensa_mask23,0,0,0)
XTREG(164,676, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum,
0,0,&xtensa_mask24,0,0,0)
XTREG(165,680, 8, 4, 4,0x2015,0x0006,-2, 6,0x1010,asid3,
0,0,&xtensa_mask25,0,0,0)
XTREG(166,684, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid2,
0,0,&xtensa_mask26,0,0,0)
XTREG(167,688, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid1,
0,0,&xtensa_mask27,0,0,0)
XTREG(168,692, 1, 4, 4,0x2018,0x0006,-2, 6,0x1010,instpgszid6,
0,0,&xtensa_mask28,0,0,0)
XTREG(169,696, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid5,
0,0,&xtensa_mask29,0,0,0)
XTREG(170,700, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid4,
0,0,&xtensa_mask30,0,0,0)
XTREG(171,704, 1, 4, 4,0x201b,0x0006,-2, 6,0x1010,datapgszid6,
0,0,&xtensa_mask31,0,0,0)
XTREG(172,708, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid5,
0,0,&xtensa_mask32,0,0,0)
XTREG(173,712, 2, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid4,
0,0,&xtensa_mask33,0,0,0)
XTREG(174,716,10, 4, 4,0x201e,0x0006,-2, 6,0x1010,ptbase,
0,0,&xtensa_mask34,0,0,0)
XTREG(175,720, 2, 4, 4,0x201f,0x0006, 0, 5,0x1010,roundmode,
0,0,&xtensa_mask35,0,0,0)
XTREG(176,724, 1, 4, 4,0x2020,0x0006, 0, 5,0x1010,invalidenable,
0,0,&xtensa_mask36,0,0,0)
XTREG(177,728, 1, 4, 4,0x2021,0x0006, 0, 5,0x1010,divzeroenable,
0,0,&xtensa_mask37,0,0,0)
XTREG(178,732, 1, 4, 4,0x2022,0x0006, 0, 5,0x1010,overflowenable,
0,0,&xtensa_mask38,0,0,0)
XTREG(179,736, 1, 4, 4,0x2023,0x0006, 0, 5,0x1010,underflowenable,
0,0,&xtensa_mask39,0,0,0)
XTREG(180,740, 1, 4, 4,0x2024,0x0006, 0, 5,0x1010,inexactenable,
0,0,&xtensa_mask40,0,0,0)
XTREG(181,744, 1, 4, 4,0x2025,0x0006, 0, 5,0x1010,invalidflag,
0,0,&xtensa_mask41,0,0,0)
XTREG(182,748, 1, 4, 4,0x2026,0x0006, 0, 5,0x1010,divzeroflag,
0,0,&xtensa_mask42,0,0,0)
XTREG(183,752, 1, 4, 4,0x2027,0x0006, 0, 5,0x1010,overflowflag,
0,0,&xtensa_mask43,0,0,0)
XTREG(184,756, 1, 4, 4,0x2028,0x0006, 0, 5,0x1010,underflowflag,
0,0,&xtensa_mask44,0,0,0)
XTREG(185,760, 1, 4, 4,0x2029,0x0006, 0, 5,0x1010,inexactflag,
0,0,&xtensa_mask45,0,0,0)
XTREG(186,764,20, 4, 4,0x202a,0x0006, 0, 5,0x1010,fpreserved20,
0,0,&xtensa_mask46,0,0,0)
XTREG(187,768,20, 4, 4,0x202b,0x0006, 0, 5,0x1010,fpreserved20a,
0,0,&xtensa_mask47,0,0,0)
XTREG(188,772, 5, 4, 4,0x202c,0x0006, 0, 5,0x1010,fpreserved5,
0,0,&xtensa_mask48,0,0,0)
XTREG_END

20758
target/xtensa/core-de233_fpu/xtensa-modules.c.inc Normal file
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/*
* Copyright (c) 2020, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/gdbstub.h"
#include "qemu-common.h"
#include "qemu/host-utils.h"
#include "core-dsp3400/core-isa.h"
#include "core-dsp3400/core-matmap.h"
#include "overlay_tool.h"
#define xtensa_modules xtensa_modules_dsp3400
#include "core-dsp3400/xtensa-modules.c.inc"
static XtensaConfig dsp3400 __attribute__((unused)) = {
.name = "dsp3400",
.gdb_regmap = {
.reg = {
#include "core-dsp3400/gdb-config.c.inc"
}
},
.isa_internal = &xtensa_modules,
.clock_freq_khz = 40000,
.opcode_translators = (const XtensaOpcodeTranslators *[]){
&xtensa_core_opcodes,
&xtensa_fpu2000_opcodes,
NULL,
},
DEFAULT_SECTIONS
};
REGISTER_CORE(dsp3400)

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/*
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
* processor CORE configuration
*
* See <xtensa/config/core.h>, which includes this file, for more details.
*/
/* Xtensa processor core configuration information.
Copyright (c) 1999-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/*
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
* configured, and a value of 0 otherwise. These macros are always defined.
*/
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 0 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 4 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
#define XCHAL_HAVE_FP 1 /* floating point pkg */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
/* In T1050, applies to selected core load and store instructions (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
#define XCHAL_SW_VERSION 800002 /* sw version of this header */
#define XCHAL_CORE_ID "dsp3400_RC2" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x0002DC22 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC3F3DBFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x1082C3B0 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 230001 /* major*100+minor */
#define XCHAL_HW_REL_LX3 1
#define XCHAL_HW_REL_LX3_0 1
#define XCHAL_HW_REL_LX3_0_1 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 230001 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 230001 /* latest targeted hw */
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 7
#define XCHAL_DCACHE_SETWIDTH 7
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 2
#define XCHAL_DCACHE_WAYS 2
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 1
#define XCHAL_DCACHE_LINE_LOCKABLE 1
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 8
#define XCHAL_DCACHE_ACCESS_SIZE 16
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x5FFE0000
#define XCHAL_INSTRAM0_PADDR 0x5FFE0000
#define XCHAL_INSTRAM0_SIZE 65536
#define XCHAL_INSTRAM0_ECC_PARITY 0
/* Instruction RAM 1: */
#define XCHAL_INSTRAM1_VADDR 0x5FFF0000
#define XCHAL_INSTRAM1_PADDR 0x5FFF0000
#define XCHAL_INSTRAM1_SIZE 65536
#define XCHAL_INSTRAM1_ECC_PARITY 0
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0x5FFD0000
#define XCHAL_DATARAM0_PADDR 0x5FFD0000
#define XCHAL_DATARAM0_SIZE 32768
#define XCHAL_DATARAM0_ECC_PARITY 0
/* Data RAM 1: */
#define XCHAL_DATARAM1_VADDR 0x5FFD8000
#define XCHAL_DATARAM1_PADDR 0x5FFD8000
#define XCHAL_DATARAM1_SIZE 32768
#define XCHAL_DATARAM1_ECC_PARITY 0
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 13 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 9 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
(not including level zero) */
#define XCHAL_EXCM_LEVEL 4 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x00001200
#define XCHAL_INTLEVEL2_MASK 0x00000980
#define XCHAL_INTLEVEL3_MASK 0x00000460
#define XCHAL_INTLEVEL4_MASK 0x00000019
#define XCHAL_INTLEVEL5_MASK 0x00000006
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00000000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00001200
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00001B80
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00001FE0
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00001FF9
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00001FFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00001FFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00001FFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 4
#define XCHAL_INT1_LEVEL 5
#define XCHAL_INT2_LEVEL 5
#define XCHAL_INT3_LEVEL 4
#define XCHAL_INT4_LEVEL 4
#define XCHAL_INT5_LEVEL 3
#define XCHAL_INT6_LEVEL 3
#define XCHAL_INT7_LEVEL 2
#define XCHAL_INT8_LEVEL 2
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 3
#define XCHAL_INT11_LEVEL 2
#define XCHAL_INT12_LEVEL 1
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_WRITE_ERROR
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFFE000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000400
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x000003FE
#define XCHAL_INTTYPE_MASK_TIMER 0x00000801
#define XCHAL_INTTYPE_MASK_NMI 0x00000000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00001000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XCHAL_TIMER0_INTERRUPT 0 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 11 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_WRITE_ERROR_INTERRUPT 12 /* write-error interrupt */
/* Interrupt numbers for levels at which only one interrupt is configured: */
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
/*
* External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
#define XCHAL_EXTINT0_NUM 1 /* (intlevel 5) */
#define XCHAL_EXTINT1_NUM 2 /* (intlevel 5) */
#define XCHAL_EXTINT2_NUM 3 /* (intlevel 4) */
#define XCHAL_EXTINT3_NUM 4 /* (intlevel 4) */
#define XCHAL_EXTINT4_NUM 5 /* (intlevel 3) */
#define XCHAL_EXTINT5_NUM 6 /* (intlevel 3) */
#define XCHAL_EXTINT6_NUM 7 /* (intlevel 2) */
#define XCHAL_EXTINT7_NUM 8 /* (intlevel 2) */
#define XCHAL_EXTINT8_NUM 9 /* (intlevel 1) */
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
number: 1 == XEA1 (old)
2 == XEA2 (new)
0 == XEAX (extern) */
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x5FFE0400 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x5FFE0400
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x5FFE0000
#define XCHAL_RESET_VECTOR0_PADDR 0x5FFE0000
#define XCHAL_RESET_VECTOR1_VADDR 0xFFFF1000
#define XCHAL_RESET_VECTOR1_PADDR 0xFFFF1000
#define XCHAL_RESET_VECTOR_VADDR 0x5FFE0000
#define XCHAL_RESET_VECTOR_PADDR 0x5FFE0000
#define XCHAL_USER_VECOFS 0x0000023C
#define XCHAL_USER_VECTOR_VADDR 0x5FFE063C
#define XCHAL_USER_VECTOR_PADDR 0x5FFE063C
#define XCHAL_KERNEL_VECOFS 0x0000021C
#define XCHAL_KERNEL_VECTOR_VADDR 0x5FFE061C
#define XCHAL_KERNEL_VECTOR_PADDR 0x5FFE061C
#define XCHAL_DOUBLEEXC_VECOFS 0x0000025C
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x5FFE065C
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x5FFE065C
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x5FFE0400
#define XCHAL_WINDOW_VECTORS_PADDR 0x5FFE0400
#define XCHAL_INTLEVEL2_VECOFS 0x0000017C
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x5FFE057C
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x5FFE057C
#define XCHAL_INTLEVEL3_VECOFS 0x0000019C
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x5FFE059C
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x5FFE059C
#define XCHAL_INTLEVEL4_VECOFS 0x000001BC
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x5FFE05BC
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x5FFE05BC
#define XCHAL_INTLEVEL5_VECOFS 0x000001DC
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x5FFE05DC
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x5FFE05DC
#define XCHAL_INTLEVEL6_VECOFS 0x000001FC
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x5FFE05FC
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x5FFE05FC
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 1 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
[autorefill] and protection)
usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* _XTENSA_CORE_CONFIGURATION_H */

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/*
* xtensa/config/core-matmap.h -- Memory access and translation mapping
* parameters (CHAL) of the Xtensa processor core configuration.
*
* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
* this file) for more details.
*
* In the Xtensa processor products released to date, all parameters
* defined in this file are derivable (at least in theory) from
* information contained in the core-isa.h header file.
* In particular, the following core configuration parameters are relevant:
* XCHAL_HAVE_CACHEATTR
* XCHAL_HAVE_MIMIC_CACHEATTR
* XCHAL_HAVE_XLT_CACHEATTR
* XCHAL_HAVE_PTP_MMU
* XCHAL_ITLB_ARF_ENTRIES_LOG2
* XCHAL_DTLB_ARF_ENTRIES_LOG2
* XCHAL_DCACHE_IS_WRITEBACK
* XCHAL_ICACHE_SIZE (presence of I-cache)
* XCHAL_DCACHE_SIZE (presence of D-cache)
* XCHAL_HW_VERSION_MAJOR
* XCHAL_HW_VERSION_MINOR
*/
/* Copyright (c) 1999-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
#define XTENSA_CONFIG_CORE_MATMAP_H
/*----------------------------------------------------------------------
CACHE (MEMORY ACCESS) ATTRIBUTES
----------------------------------------------------------------------*/
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_BYPASS XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_CACHED XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION XCHAL_SEP \
XTHAL_FAM_EXCEPTION
#define XCHAL_LCA_LIST XTHAL_LAM_CACHED_NOALLOC XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_BYPASSG XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_CACHED XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_EXCEPTION XCHAL_SEP \
XTHAL_LAM_ISOLATE XCHAL_SEP \
XTHAL_LAM_EXCEPTION
#define XCHAL_SCA_LIST XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_WRITETHRU XCHAL_SEP \
XTHAL_SAM_BYPASS XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_WRITEBACK XCHAL_SEP \
XTHAL_SAM_WRITEBACK_NOALLOC XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_EXCEPTION XCHAL_SEP \
XTHAL_SAM_ISOLATE XCHAL_SEP \
XTHAL_SAM_EXCEPTION
/*
* Specific encoded cache attribute values of general interest.
* If a specific cache mode is not available, the closest available
* one is returned instead (eg. writethru instead of writeback,
* bypass instead of writethru).
*/
#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */
#define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
#define XCHAL_CA_WRITEBACK 4 /* cache enabled (write-back) mode */
#define XCHAL_CA_WRITEBACK_NOALLOC 4 /* cache enabled (write-back no-allocate) mode */
#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
#define XCHAL_CA_ISOLATE 14 /* cache isolate (accesses go to cache not memory) mode */
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
/*
* General notes on MMU parameters.
*
* Terminology:
* ASID = address-space ID (acts as an "extension" of virtual addresses)
* VPN = virtual page number
* PPN = physical page number
* CA = encoded cache attribute (access modes)
* TLB = translation look-aside buffer (term is stretched somewhat here)
* I = instruction (fetch accesses)
* D = data (load and store accesses)
* way = each TLB (ITLB and DTLB) consists of a number of "ways"
* that simultaneously match the virtual address of an access;
* a TLB successfully translates a virtual address if exactly
* one way matches the vaddr; if none match, it is a miss;
* if multiple match, one gets a "multihit" exception;
* each way can be independently configured in terms of number of
* entries, page sizes, which fields are writable or constant, etc.
* set = group of contiguous ways with exactly identical parameters
* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
* from the page table and storing it in one of the auto-refill ways;
* if this PTE load also misses, a miss exception is posted for s/w.
* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
* page arbitrarily under program control; it has a single entry,
* is non-auto-refill (some other way(s) must be auto-refill),
* all its fields (VPN, PPN, ASID, CA) are all writable, and it
* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
* restriction is that this be the only page size it supports).
*
* TLB way entries are virtually indexed.
* TLB ways that support multiple page sizes:
* - must have all writable VPN and PPN fields;
* - can only use one page size at any given time (eg. setup at startup),
* selected by the respective ITLBCFG or DTLBCFG special register,
* whose bits n*4+3 .. n*4 index the list of page sizes for way n
* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
* this list may be sparse for auto-refill ways because auto-refill
* ways have independent lists of supported page sizes sharing a
* common encoding with PTE entries; the encoding is the index into
* this list; unsupported sizes for a given way are zero in the list;
* selecting unsupported sizes results in undefined hardware behaviour;
* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
*/
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */
/*** Instruction TLB: ***/
#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_ITLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* ITLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000
/* Reset PPN values for each entry of ITLB way set 0 (because SET0_PPN_RESET is non-zero): */
#define XCHAL_ITLB_SET0_E0_PPN_RESET 0x00000000
#define XCHAL_ITLB_SET0_E1_PPN_RESET 0x20000000
#define XCHAL_ITLB_SET0_E2_PPN_RESET 0x40000000
#define XCHAL_ITLB_SET0_E3_PPN_RESET 0x60000000
#define XCHAL_ITLB_SET0_E4_PPN_RESET 0x80000000
#define XCHAL_ITLB_SET0_E5_PPN_RESET 0xA0000000
#define XCHAL_ITLB_SET0_E6_PPN_RESET 0xC0000000
#define XCHAL_ITLB_SET0_E7_PPN_RESET 0xE0000000
/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02
#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02
/*** Data TLB: ***/
#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */
#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */
#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */
/* Way set to which each way belongs: */
#define XCHAL_DTLB_WAY0_SET 0
/* Ways sets that are used by hardware auto-refill (ARF): */
#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */
/* Way sets that are "min-wired" (see terminology comment above): */
#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
/* DTLB way set 0 (group of ways 0 thru 0): */
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */
#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP;
2^PAGESZ_BITS entries in list, unsupported entries are zero */
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */
#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000
#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000
#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000
#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000
#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000
#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000
#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000
#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000
/* Reset PPN values for each entry of DTLB way set 0 (because SET0_PPN_RESET is non-zero): */
#define XCHAL_DTLB_SET0_E0_PPN_RESET 0x00000000
#define XCHAL_DTLB_SET0_E1_PPN_RESET 0x20000000
#define XCHAL_DTLB_SET0_E2_PPN_RESET 0x40000000
#define XCHAL_DTLB_SET0_E3_PPN_RESET 0x60000000
#define XCHAL_DTLB_SET0_E4_PPN_RESET 0x80000000
#define XCHAL_DTLB_SET0_E5_PPN_RESET 0xA0000000
#define XCHAL_DTLB_SET0_E6_PPN_RESET 0xC0000000
#define XCHAL_DTLB_SET0_E7_PPN_RESET 0xE0000000
/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */
#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02
#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/

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/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
Copyright (c) 2003-2010 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
XTREG( 46,184,32, 4, 4,0x0300,0x000e,-1, 3,0x0210,expstate, 0,0,0,0,0,0)
XTREG( 47,188,32, 4, 4,0x0030,0x0006, 0, 4,0x0401,f0,
"03:03:44:00","03:03:04:00",0,0,0,0)
XTREG( 48,192,32, 4, 4,0x0031,0x0006, 0, 4,0x0401,f1,
"03:13:44:00","03:13:04:00",0,0,0,0)
XTREG( 49,196,32, 4, 4,0x0032,0x0006, 0, 4,0x0401,f2,
"03:23:44:00","03:23:04:00",0,0,0,0)
XTREG( 50,200,32, 4, 4,0x0033,0x0006, 0, 4,0x0401,f3,
"03:33:44:00","03:33:04:00",0,0,0,0)
XTREG( 51,204,32, 4, 4,0x0034,0x0006, 0, 4,0x0401,f4,
"03:43:44:00","03:43:04:00",0,0,0,0)
XTREG( 52,208,32, 4, 4,0x0035,0x0006, 0, 4,0x0401,f5,
"03:53:44:00","03:53:04:00",0,0,0,0)
XTREG( 53,212,32, 4, 4,0x0036,0x0006, 0, 4,0x0401,f6,
"03:63:44:00","03:63:04:00",0,0,0,0)
XTREG( 54,216,32, 4, 4,0x0037,0x0006, 0, 4,0x0401,f7,
"03:73:44:00","03:73:04:00",0,0,0,0)
XTREG( 55,220,32, 4, 4,0x0038,0x0006, 0, 4,0x0401,f8,
"03:83:44:00","03:83:04:00",0,0,0,0)
XTREG( 56,224,32, 4, 4,0x0039,0x0006, 0, 4,0x0401,f9,
"03:93:44:00","03:93:04:00",0,0,0,0)
XTREG( 57,228,32, 4, 4,0x003a,0x0006, 0, 4,0x0401,f10,
"03:a3:44:00","03:a3:04:00",0,0,0,0)
XTREG( 58,232,32, 4, 4,0x003b,0x0006, 0, 4,0x0401,f11,
"03:b3:44:00","03:b3:04:00",0,0,0,0)
XTREG( 59,236,32, 4, 4,0x003c,0x0006, 0, 4,0x0401,f12,
"03:c3:44:00","03:c3:04:00",0,0,0,0)
XTREG( 60,240,32, 4, 4,0x003d,0x0006, 0, 4,0x0401,f13,
"03:d3:44:00","03:d3:04:00",0,0,0,0)
XTREG( 61,244,32, 4, 4,0x003e,0x0006, 0, 4,0x0401,f14,
"03:e3:44:00","03:e3:04:00",0,0,0,0)
XTREG( 62,248,32, 4, 4,0x003f,0x0006, 0, 4,0x0401,f15,
"03:f3:44:00","03:f3:04:00",0,0,0,0)
XTREG( 63,252,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0)
XTREG( 64,256,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0)
XTREG( 65,260, 4, 4, 4,0x0301,0x0006, 2, 3,0x0210,sov, 0,0,0,0,0,0)
XTREG( 66,264, 1, 4, 4,0x0302,0x0006, 2, 3,0x0210,sat_mode, 0,0,0,0,0,0)
XTREG( 67,268, 6, 4, 4,0x0303,0x0006, 2, 3,0x0210,sar0, 0,0,0,0,0,0)
XTREG( 68,272, 6, 4, 4,0x0304,0x0006, 2, 3,0x0210,sar1, 0,0,0,0,0,0)
XTREG( 69,276, 6, 4, 4,0x0305,0x0006, 2, 3,0x0210,sar2, 0,0,0,0,0,0)
XTREG( 70,280, 6, 4, 4,0x0306,0x0006, 2, 3,0x0210,sar3, 0,0,0,0,0,0)
XTREG( 71,284, 6, 4, 4,0x0307,0x0006, 2, 3,0x0210,hsar0, 0,0,0,0,0,0)
XTREG( 72,288, 6, 4, 4,0x0308,0x0006, 2, 3,0x0210,hsar1, 0,0,0,0,0,0)
XTREG( 73,292, 6, 4, 4,0x0309,0x0006, 2, 3,0x0210,hsar2, 0,0,0,0,0,0)
XTREG( 74,296, 6, 4, 4,0x030a,0x0006, 2, 3,0x0210,hsar3, 0,0,0,0,0,0)
XTREG( 75,300,32, 4, 4,0x030b,0x0006, 2, 3,0x0200,max_reg_0, 0,0,0,0,0,0)
XTREG( 76,304,32, 4, 4,0x030c,0x0006, 2, 3,0x0200,max_reg_1, 0,0,0,0,0,0)
XTREG( 77,308,32, 4, 4,0x030d,0x0006, 2, 3,0x0200,max_reg_2, 0,0,0,0,0,0)
XTREG( 78,312,32, 4, 4,0x030e,0x0006, 2, 3,0x0200,max_reg_3, 0,0,0,0,0,0)
XTREG( 79,316,32, 4, 4,0x030f,0x0006, 2, 3,0x0200,arg_max_reg_0,0,0,0,0,0,0)
XTREG( 80,320,32, 4, 4,0x0310,0x0006, 2, 3,0x0200,arg_max_reg_1,0,0,0,0,0,0)
XTREG( 81,324,32, 4, 4,0x0311,0x0006, 2, 3,0x0200,arg_max_reg_2,0,0,0,0,0,0)
XTREG( 82,328,32, 4, 4,0x0312,0x0006, 2, 3,0x0200,arg_max_reg_3,0,0,0,0,0,0)
XTREG( 83,332,32, 4, 4,0x0313,0x0006, 2, 3,0x0200,nco_counter_0,0,0,0,0,0,0)
XTREG( 84,336,32, 4, 4,0x0314,0x0006, 2, 3,0x0200,nco_counter_1,0,0,0,0,0,0)
XTREG( 85,340,32, 4, 4,0x0315,0x0006, 2, 3,0x0200,nco_counter_2,0,0,0,0,0,0)
XTREG( 86,344,32, 4, 4,0x0316,0x0006, 2, 3,0x0200,nco_counter_3,0,0,0,0,0,0)
XTREG( 87,348, 4, 4, 4,0x0317,0x0006, 2, 3,0x0210,interp_ext_n,0,0,0,0,0,0)
XTREG( 88,352, 4, 4, 4,0x0318,0x0006, 2, 3,0x0210,interp_ext_l,0,0,0,0,0,0)
XTREG( 89,356,32, 4, 4,0x0319,0x0006, 2, 3,0x0200,llr_buf_0, 0,0,0,0,0,0)
XTREG( 90,360,32, 4, 4,0x031a,0x0006, 2, 3,0x0200,llr_buf_1, 0,0,0,0,0,0)
XTREG( 91,364,32, 4, 4,0x031b,0x0006, 2, 3,0x0200,llr_buf_2, 0,0,0,0,0,0)
XTREG( 92,368,32, 4, 4,0x031c,0x0006, 2, 3,0x0200,llr_buf_3, 0,0,0,0,0,0)
XTREG( 93,372,32, 4, 4,0x031d,0x0006, 2, 3,0x0200,llr_buf_4, 0,0,0,0,0,0)
XTREG( 94,376,32, 4, 4,0x031e,0x0006, 2, 3,0x0200,llr_buf_5, 0,0,0,0,0,0)
XTREG( 95,380,32, 4, 4,0x031f,0x0006, 2, 3,0x0200,llr_buf_6, 0,0,0,0,0,0)
XTREG( 96,384,32, 4, 4,0x0320,0x0006, 2, 3,0x0200,llr_buf_7, 0,0,0,0,0,0)
XTREG( 97,388,32, 4, 4,0x0321,0x0006, 2, 3,0x0200,llr_buf_8, 0,0,0,0,0,0)
XTREG( 98,392,32, 4, 4,0x0322,0x0006, 2, 3,0x0200,llr_buf_9, 0,0,0,0,0,0)
XTREG( 99,396,32, 4, 4,0x0323,0x0006, 2, 3,0x0200,llr_buf_10, 0,0,0,0,0,0)
XTREG(100,400,32, 4, 4,0x0324,0x0006, 2, 3,0x0200,llr_buf_11, 0,0,0,0,0,0)
XTREG(101,404,32, 4, 4,0x0325,0x0006, 2, 3,0x0200,llr_buf_12, 0,0,0,0,0,0)
XTREG(102,408,32, 4, 4,0x0326,0x0006, 2, 3,0x0200,llr_buf_13, 0,0,0,0,0,0)
XTREG(103,412,32, 4, 4,0x0327,0x0006, 2, 3,0x0200,llr_buf_14, 0,0,0,0,0,0)
XTREG(104,416,32, 4, 4,0x0328,0x0006, 2, 3,0x0200,llr_buf_15, 0,0,0,0,0,0)
XTREG(105,420,32, 4, 4,0x0329,0x0006, 2, 3,0x0200,llr_buf_16, 0,0,0,0,0,0)
XTREG(106,424,32, 4, 4,0x032a,0x0006, 2, 3,0x0200,llr_buf_17, 0,0,0,0,0,0)
XTREG(107,428,32, 4, 4,0x032b,0x0006, 2, 3,0x0200,llr_buf_18, 0,0,0,0,0,0)
XTREG(108,432,32, 4, 4,0x032c,0x0006, 2, 3,0x0200,llr_buf_19, 0,0,0,0,0,0)
XTREG(109,436,32, 4, 4,0x032d,0x0006, 2, 3,0x0200,llr_buf_20, 0,0,0,0,0,0)
XTREG(110,440,32, 4, 4,0x032e,0x0006, 2, 3,0x0200,llr_buf_21, 0,0,0,0,0,0)
XTREG(111,444,32, 4, 4,0x032f,0x0006, 2, 3,0x0200,llr_buf_22, 0,0,0,0,0,0)
XTREG(112,448,32, 4, 4,0x0330,0x0006, 2, 3,0x0200,llr_buf_23, 0,0,0,0,0,0)
XTREG(113,452,32, 4, 4,0x0331,0x0006, 2, 3,0x0200,smod_buf_0, 0,0,0,0,0,0)
XTREG(114,456,32, 4, 4,0x0332,0x0006, 2, 3,0x0200,smod_buf_1, 0,0,0,0,0,0)
XTREG(115,460,32, 4, 4,0x0333,0x0006, 2, 3,0x0200,smod_buf_2, 0,0,0,0,0,0)
XTREG(116,464,32, 4, 4,0x0334,0x0006, 2, 3,0x0200,smod_buf_3, 0,0,0,0,0,0)
XTREG(117,468,32, 4, 4,0x0335,0x0006, 2, 3,0x0200,smod_buf_4, 0,0,0,0,0,0)
XTREG(118,472,32, 4, 4,0x0336,0x0006, 2, 3,0x0200,smod_buf_5, 0,0,0,0,0,0)
XTREG(119,476,32, 4, 4,0x0337,0x0006, 2, 3,0x0200,smod_buf_6, 0,0,0,0,0,0)
XTREG(120,480,32, 4, 4,0x0338,0x0006, 2, 3,0x0200,smod_buf_7, 0,0,0,0,0,0)
XTREG(121,484, 8, 4, 4,0x0339,0x0006, 2, 3,0x0210,weight_reg, 0,0,0,0,0,0)
XTREG(122,488, 5, 4, 4,0x033a,0x0006, 2, 3,0x0210,scale_reg, 0,0,0,0,0,0)
XTREG(123,492, 6, 4, 4,0x033b,0x0006, 2, 3,0x0210,llr_pos, 0,0,0,0,0,0)
XTREG(124,496, 7, 4, 4,0x033c,0x0006, 2, 3,0x0210,smod_pos, 0,0,0,0,0,0)
XTREG(125,500,32, 4, 4,0x033d,0x0006, 2, 3,0x0210,perm_reg, 0,0,0,0,0,0)
XTREG(126,504,32, 4, 4,0x033e,0x0006, 2, 3,0x0200,smod_offset_table_0,0,0,0,0,0,0)
XTREG(127,508,32, 4, 4,0x033f,0x0006, 2, 3,0x0200,smod_offset_table_1,0,0,0,0,0,0)
XTREG(128,512,32, 4, 4,0x0340,0x0006, 2, 3,0x0200,smod_offset_table_2,0,0,0,0,0,0)
XTREG(129,516,32, 4, 4,0x0341,0x0006, 2, 3,0x0200,smod_offset_table_3,0,0,0,0,0,0)
XTREG(130,520, 4, 4, 4,0x0342,0x0006, 2, 3,0x0210,phasor_n, 0,0,0,0,0,0)
XTREG(131,524,16, 4, 4,0x0343,0x0006, 2, 3,0x0210,phasor_offset,0,0,0,0,0,0)
XTREG(132,528,320,64,16,0x1008,0x0006, 2, 4,0x0201,acu0,
"03:00:84:f8:03:10:84:8d:03:20:84:9d:03:30:84:ac","03:43:20:08:03:43:28:03:03:43:20:33:03:43:28:25",0,0,0,0)
XTREG(133,592,320,64,16,0x1009,0x0006, 2, 4,0x0201,acu1,
"03:00:94:f8:03:10:94:8d:03:20:94:9d:03:30:94:ac","03:43:21:08:03:43:29:03:03:43:21:33:03:43:29:25",0,0,0,0)
XTREG(134,656,320,64,16,0x100a,0x0006, 2, 4,0x0201,acu2,
"03:00:a4:f8:03:10:a4:8d:03:20:a4:9d:03:30:a4:ac","03:43:22:08:03:43:2a:03:03:43:22:33:03:43:2a:25",0,0,0,0)
XTREG(135,720,320,64,16,0x100b,0x0006, 2, 4,0x0201,acu3,
"03:00:b4:f8:03:10:b4:8d:03:20:b4:9d:03:30:b4:ac","03:43:23:08:03:43:2b:03:03:43:23:33:03:43:2b:25",0,0,0,0)
XTREG(136,784,320,64,16,0x100c,0x0006, 2, 4,0x0201,acu4,
"03:00:c4:f8:03:10:c4:8d:03:20:c4:9d:03:30:c4:ac","03:43:24:08:03:43:2c:03:03:43:24:33:03:43:2c:25",0,0,0,0)
XTREG(137,848,320,64,16,0x100d,0x0006, 2, 4,0x0201,acu5,
"03:00:d4:f8:03:10:d4:8d:03:20:d4:9d:03:30:d4:ac","03:43:25:08:03:43:2d:03:03:43:25:33:03:43:2d:25",0,0,0,0)
XTREG(138,912,320,64,16,0x100e,0x0006, 2, 4,0x0201,acu6,
"03:00:e4:f8:03:10:e4:8d:03:20:e4:9d:03:30:e4:ac","03:43:26:08:03:43:2e:03:03:43:26:33:03:43:2e:25",0,0,0,0)
XTREG(139,976,320,64,16,0x100f,0x0006, 2, 4,0x0201,acu7,
"03:00:f4:f8:03:10:f4:8d:03:20:f4:9d:03:30:f4:ac","03:43:27:08:03:43:2f:03:03:43:27:33:03:43:2f:25",0,0,0,0)
XTREG(140,1040,128,16,16,0x1010,0x0006, 2, 4,0x0201,cm0,
"03:00:04:5d","03:40:03:07",0,0,0,0)
XTREG(141,1056,128,16,16,0x1011,0x0006, 2, 4,0x0201,cm1,
"03:00:14:5d","03:40:13:07",0,0,0,0)
XTREG(142,1072,128,16,16,0x1012,0x0006, 2, 4,0x0201,cm2,
"03:00:24:5d","03:40:23:07",0,0,0,0)
XTREG(143,1088,128,16,16,0x1013,0x0006, 2, 4,0x0201,cm3,
"03:00:34:5d","03:40:33:07",0,0,0,0)
XTREG(144,1104,128,16,16,0x1014,0x0006, 2, 4,0x0201,cm4,
"03:00:44:5d","03:40:43:07",0,0,0,0)
XTREG(145,1120,128,16,16,0x1015,0x0006, 2, 4,0x0201,cm5,
"03:00:54:5d","03:40:53:07",0,0,0,0)
XTREG(146,1136,128,16,16,0x1016,0x0006, 2, 4,0x0201,cm6,
"03:00:64:5d","03:40:63:07",0,0,0,0)
XTREG(147,1152,128,16,16,0x1017,0x0006, 2, 4,0x0201,cm7,
"03:00:74:5d","03:40:73:07",0,0,0,0)
XTREG(148,1168,128,16,16,0x1018,0x0006, 2, 4,0x0201,cm8,
"03:00:84:5d","03:40:83:07",0,0,0,0)
XTREG(149,1184,128,16,16,0x1019,0x0006, 2, 4,0x0201,cm9,
"03:00:94:5d","03:40:93:07",0,0,0,0)
XTREG(150,1200,128,16,16,0x101a,0x0006, 2, 4,0x0201,cm10,
"03:00:a4:5d","03:40:a3:07",0,0,0,0)
XTREG(151,1216,128,16,16,0x101b,0x0006, 2, 4,0x0201,cm11,
"03:00:b4:5d","03:40:b3:07",0,0,0,0)
XTREG(152,1232,128,16,16,0x101c,0x0006, 2, 4,0x0201,cm12,
"03:00:c4:5d","03:40:c3:07",0,0,0,0)
XTREG(153,1248,128,16,16,0x101d,0x0006, 2, 4,0x0201,cm13,
"03:00:d4:5d","03:40:d3:07",0,0,0,0)
XTREG(154,1264,128,16,16,0x101e,0x0006, 2, 4,0x0201,cm14,
"03:00:e4:5d","03:40:e3:07",0,0,0,0)
XTREG(155,1280,128,16,16,0x101f,0x0006, 2, 4,0x0201,cm15,
"03:00:f4:5d","03:40:f3:07",0,0,0,0)
XTREG(156,1296,256,32,16,0x1020,0x0006, 2, 4,0x0201,pq0,
"03:00:04:7c:03:10:04:cc","03:40:02:07:03:40:0c:07",0,0,0,0)
XTREG(157,1328,256,32,16,0x1021,0x0006, 2, 4,0x0201,pq1,
"03:00:14:7c:03:10:14:cc","03:40:12:07:03:40:1c:07",0,0,0,0)
XTREG(158,1360,256,32,16,0x1022,0x0006, 2, 4,0x0201,pq2,
"03:00:24:7c:03:10:24:cc","03:40:22:07:03:40:2c:07",0,0,0,0)
XTREG(159,1392,256,32,16,0x1023,0x0006, 2, 4,0x0201,pq3,
"03:00:34:7c:03:10:34:cc","03:40:32:07:03:40:3c:07",0,0,0,0)
XTREG(160,1424,256,32,16,0x1024,0x0006, 2, 4,0x0201,pq4,
"03:00:44:7c:03:10:44:cc","03:40:42:07:03:40:4c:07",0,0,0,0)
XTREG(161,1456,256,32,16,0x1025,0x0006, 2, 4,0x0201,pq5,
"03:00:54:7c:03:10:54:cc","03:40:52:07:03:40:5c:07",0,0,0,0)
XTREG(162,1488,256,32,16,0x1026,0x0006, 2, 4,0x0201,pq6,
"03:00:64:7c:03:10:64:cc","03:40:62:07:03:40:6c:07",0,0,0,0)
XTREG(163,1520,256,32,16,0x1027,0x0006, 2, 4,0x0201,pq7,
"03:00:74:7c:03:10:74:cc","03:40:72:07:03:40:7c:07",0,0,0,0)
XTREG(164,1552,256,32,16,0x1028,0x0006, 2, 4,0x0201,pq8,
"03:00:84:7c:03:10:84:cc","03:40:82:07:03:40:8c:07",0,0,0,0)
XTREG(165,1584,256,32,16,0x1029,0x0006, 2, 4,0x0201,pq9,
"03:00:94:7c:03:10:94:cc","03:40:92:07:03:40:9c:07",0,0,0,0)
XTREG(166,1616,256,32,16,0x102a,0x0006, 2, 4,0x0201,pq10,
"03:00:a4:7c:03:10:a4:cc","03:40:a2:07:03:40:ac:07",0,0,0,0)
XTREG(167,1648,256,32,16,0x102b,0x0006, 2, 4,0x0201,pq11,
"03:00:b4:7c:03:10:b4:cc","03:40:b2:07:03:40:bc:07",0,0,0,0)
XTREG(168,1680,256,32,16,0x102c,0x0006, 2, 4,0x0201,pq12,
"03:00:c4:7c:03:10:c4:cc","03:40:c2:07:03:40:cc:07",0,0,0,0)
XTREG(169,1712,256,32,16,0x102d,0x0006, 2, 4,0x0201,pq13,
"03:00:d4:7c:03:10:d4:cc","03:40:d2:07:03:40:dc:07",0,0,0,0)
XTREG(170,1744,256,32,16,0x102e,0x0006, 2, 4,0x0201,pq14,
"03:00:e4:7c:03:10:e4:cc","03:40:e2:07:03:40:ec:07",0,0,0,0)
XTREG(171,1776,256,32,16,0x102f,0x0006, 2, 4,0x0201,pq15,
"03:00:f4:7c:03:10:f4:cc","03:40:f2:07:03:40:fc:07",0,0,0,0)
XTREG(172,1808,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
XTREG(173,1812, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
XTREG(174,1816, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
XTREG(175,1820,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
XTREG(176,1824,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
XTREG(177,1828,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
XTREG(178,1832,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
XTREG(179,1836,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
XTREG(180,1840,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
XTREG(181,1844,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
XTREG(182,1848,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
XTREG(183,1852,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
XTREG(184,1856,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
XTREG(185,1860,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
XTREG(186,1864,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
XTREG(187,1868,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
XTREG(188,1872,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
XTREG(189,1876,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
XTREG(190,1880,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
XTREG(191,1884,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
XTREG(192,1888,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
XTREG(193,1892,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
XTREG(194,1896,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
XTREG(195,1900,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
XTREG(196,1904,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
XTREG(197,1908,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
XTREG(198,1912,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
XTREG(199,1916,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
XTREG(200,1920, 4, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
XTREG(201,1924,13, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
XTREG(202,1928,13, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
XTREG(203,1932,13, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
XTREG(204,1936,13, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
XTREG(205,1940,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
XTREG(206,1944, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
XTREG(207,1948,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
XTREG(208,1952,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
XTREG(209,1956,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
XTREG(210,1960,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
XTREG(211,1964, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
XTREG(212,1968,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
XTREG(213,1972,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
XTREG(214,1976,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
XTREG(215,1980,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
XTREG(216,1984,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
XTREG(217,1988,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
XTREG(218,1992,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
XTREG(219,1996,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
XTREG(220,2000,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
XTREG(221,2004,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
XTREG(222,2008,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
XTREG(223,2012,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
XTREG(224,2016,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
XTREG(225,2020,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
XTREG(226,2024,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
XTREG(227,2028,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
XTREG(228,2032,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
XTREG(229,2036,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
XTREG(230,2040,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
XTREG(231,2044, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
0,0,&xtensa_mask0,0,0,0)
XTREG(232,2045, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
0,0,&xtensa_mask1,0,0,0)
XTREG(233,2046, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
0,0,&xtensa_mask2,0,0,0)
XTREG(234,2047, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
0,0,&xtensa_mask3,0,0,0)
XTREG(235,2048, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
0,0,&xtensa_mask4,0,0,0)
XTREG(236,2049, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
0,0,&xtensa_mask5,0,0,0)
XTREG(237,2050, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
0,0,&xtensa_mask6,0,0,0)
XTREG(238,2051, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
0,0,&xtensa_mask7,0,0,0)
XTREG(239,2052, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
0,0,&xtensa_mask8,0,0,0)
XTREG(240,2053, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
0,0,&xtensa_mask9,0,0,0)
XTREG(241,2054, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
0,0,&xtensa_mask10,0,0,0)
XTREG(242,2055, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
0,0,&xtensa_mask11,0,0,0)
XTREG(243,2056, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
0,0,&xtensa_mask12,0,0,0)
XTREG(244,2057, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
0,0,&xtensa_mask13,0,0,0)
XTREG(245,2058, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
0,0,&xtensa_mask14,0,0,0)
XTREG(246,2059, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
0,0,&xtensa_mask15,0,0,0)
XTREG(247,2060, 4, 4, 4,0x2007,0x0006,-2, 6,0x1010,psintlevel,
0,0,&xtensa_mask16,0,0,0)
XTREG(248,2064, 1, 4, 4,0x2008,0x0006,-2, 6,0x1010,psum,
0,0,&xtensa_mask17,0,0,0)
XTREG(249,2068, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,pswoe,
0,0,&xtensa_mask18,0,0,0)
XTREG(250,2072, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,psexcm,
0,0,&xtensa_mask19,0,0,0)
XTREG(251,2076, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,pscallinc,
0,0,&xtensa_mask20,0,0,0)
XTREG(252,2080, 4, 4, 4,0x200c,0x0006,-2, 6,0x1010,psowb,
0,0,&xtensa_mask21,0,0,0)
XTREG(253,2084,20, 4, 4,0x200d,0x0006,-2, 6,0x1010,litbaddr,
0,0,&xtensa_mask22,0,0,0)
XTREG(254,2088, 1, 4, 4,0x200e,0x0006,-2, 6,0x1010,litben,
0,0,&xtensa_mask23,0,0,0)
XTREG(255,2092, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
0,0,&xtensa_mask24,0,0,0)
XTREG(256,2096, 2, 4, 4,0x2014,0x0006, 0, 5,0x1010,roundmode,
0,0,&xtensa_mask25,0,0,0)
XTREG(257,2100, 1, 4, 4,0x2015,0x0006, 0, 5,0x1010,invalidenable,
0,0,&xtensa_mask26,0,0,0)
XTREG(258,2104, 1, 4, 4,0x2016,0x0006, 0, 5,0x1010,divzeroenable,
0,0,&xtensa_mask27,0,0,0)
XTREG(259,2108, 1, 4, 4,0x2017,0x0006, 0, 5,0x1010,overflowenable,
0,0,&xtensa_mask28,0,0,0)
XTREG(260,2112, 1, 4, 4,0x2018,0x0006, 0, 5,0x1010,underflowenable,
0,0,&xtensa_mask29,0,0,0)
XTREG(261,2116, 1, 4, 4,0x2019,0x0006, 0, 5,0x1010,inexactenable,
0,0,&xtensa_mask30,0,0,0)
XTREG(262,2120, 1, 4, 4,0x201a,0x0006, 0, 5,0x1010,invalidflag,
0,0,&xtensa_mask31,0,0,0)
XTREG(263,2124, 1, 4, 4,0x201b,0x0006, 0, 5,0x1010,divzeroflag,
0,0,&xtensa_mask32,0,0,0)
XTREG(264,2128, 1, 4, 4,0x201c,0x0006, 0, 5,0x1010,overflowflag,
0,0,&xtensa_mask33,0,0,0)
XTREG(265,2132, 1, 4, 4,0x201d,0x0006, 0, 5,0x1010,underflowflag,
0,0,&xtensa_mask34,0,0,0)
XTREG(266,2136, 1, 4, 4,0x201e,0x0006, 0, 5,0x1010,inexactflag,
0,0,&xtensa_mask35,0,0,0)
XTREG(267,2140,20, 4, 4,0x201f,0x0006, 0, 5,0x1010,fpreserved20,
0,0,&xtensa_mask36,0,0,0)
XTREG(268,2144,20, 4, 4,0x2020,0x0006, 0, 5,0x1010,fpreserved20a,
0,0,&xtensa_mask37,0,0,0)
XTREG(269,2148, 5, 4, 4,0x2021,0x0006, 0, 5,0x1010,fpreserved5,
0,0,&xtensa_mask38,0,0,0)
XTREG(270,2152, 7, 4, 4,0x2022,0x0006, 0, 5,0x1010,fpreserved7,
0,0,&xtensa_mask39,0,0,0)
XTREG(271,2156,128,16, 4,0x2023,0x0006, 2, 5,0x0210,max_reg,
0,0,&xtensa_mask40,0,0,0)
XTREG(272,2172,128,16, 4,0x2024,0x0006, 2, 5,0x0210,arg_max_reg,
0,0,&xtensa_mask41,0,0,0)
XTREG(273,2188,128,16, 4,0x2025,0x0006, 2, 5,0x0210,nco_counter,
0,0,&xtensa_mask42,0,0,0)
XTREG(274,2204,768,96, 4,0x2026,0x0006, 2, 5,0x0210,llr_buf,
0,0,&xtensa_mask43,0,0,0)
XTREG(275,2300,256,32, 4,0x2027,0x0006, 2, 5,0x0210,smod_buf,
0,0,&xtensa_mask44,0,0,0)
XTREG_END

171906
target/xtensa/core-dsp3400/xtensa-modules.c.inc Normal file
View File

File diff suppressed because it is too large Load Diff

5
target/xtensa/cpu.c
View File

@ -31,6 +31,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "fpu/softfloat.h"
#include "qemu/module.h"
#include "migration/vmstate.h"
@ -73,6 +74,8 @@ static void xtensa_cpu_reset(DeviceState *dev)
XtensaCPU *cpu = XTENSA_CPU(s);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
CPUXtensaState *env = &cpu->env;
bool dfpu = xtensa_option_enabled(env->config,
XTENSA_OPTION_DFP_COPROCESSOR);
xcc->parent_reset(dev);
@ -104,6 +107,8 @@ static void xtensa_cpu_reset(DeviceState *dev)
reset_mmu(env);
s->halted = env->runstall;
#endif
set_no_signaling_nans(!dfpu, &env->fp_status);
set_use_first_nan(!dfpu, &env->fp_status);
}
static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)

14
target/xtensa/cpu.h
View File

@ -52,6 +52,8 @@ enum {
XTENSA_OPTION_COPROCESSOR,
XTENSA_OPTION_BOOLEAN,
XTENSA_OPTION_FP_COPROCESSOR,
XTENSA_OPTION_DFP_COPROCESSOR,
XTENSA_OPTION_DFPU_SINGLE_ONLY,
XTENSA_OPTION_MP_SYNCHRO,
XTENSA_OPTION_CONDITIONAL_STORE,
XTENSA_OPTION_ATOMCTL,
@ -359,14 +361,12 @@ typedef struct opcode_arg {
uint32_t raw_imm;
void *in;
void *out;
uint32_t num_bits;
} OpcodeArg;
typedef struct DisasContext DisasContext;
typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[]);
typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc,
const OpcodeArg arg[],
const uint32_t par[]);
typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc,
const OpcodeArg arg[],
const uint32_t par[]);
@ -408,7 +408,7 @@ enum {
typedef struct XtensaOpcodeOps {
const void *name;
XtensaOpcodeOp translate;
XtensaOpcodeBoolTest test_ill;
XtensaOpcodeUintTest test_exceptions;
XtensaOpcodeUintTest test_overflow;
const uint32_t *par;
uint32_t op_flags;
@ -422,6 +422,7 @@ typedef struct XtensaOpcodeTranslators {
extern const XtensaOpcodeTranslators xtensa_core_opcodes;
extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
extern const XtensaOpcodeTranslators xtensa_fpu_opcodes;
struct XtensaConfig {
const char *name;
@ -436,6 +437,7 @@ struct XtensaConfig {
uint32_t exception_vector[EXC_MAX];
unsigned ninterrupt;
unsigned nlevel;
unsigned nmi_level;
uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
uint32_t inttype_mask[INTTYPE_MAX];
@ -483,6 +485,8 @@ struct XtensaConfig {
unsigned n_mpu_fg_segments;
unsigned n_mpu_bg_segments;
const xtensa_mpu_entry *mpu_bg;
bool use_first_nan;
};
typedef struct XtensaConfigList {
@ -600,7 +604,7 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
void xtensa_collect_sr_names(const XtensaConfig *config);
void xtensa_translate_init(void);
void **xtensa_get_regfile_by_name(const char *name);
void **xtensa_get_regfile_by_name(const char *name, int entries, int bits);
void xtensa_breakpoint_handler(CPUState *cs);
void xtensa_register_core(XtensaConfigList *node);
void xtensa_sim_open_console(Chardev *chr);

23
target/xtensa/exc_helper.c
View File

@ -132,11 +132,15 @@ void HELPER(intset)(CPUXtensaState *env, uint32_t v)
v & env->config->inttype_mask[INTTYPE_SOFTWARE]);
}
static void intclear(CPUXtensaState *env, uint32_t v)
{
atomic_and(&env->sregs[INTSET], ~v);
}
void HELPER(intclear)(CPUXtensaState *env, uint32_t v)
{
atomic_and(&env->sregs[INTSET],
~(v & (env->config->inttype_mask[INTTYPE_SOFTWARE] |
env->config->inttype_mask[INTTYPE_EDGE])));
intclear(env, v & (env->config->inttype_mask[INTTYPE_SOFTWARE] |
env->config->inttype_mask[INTTYPE_EDGE]));
}
static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
@ -159,11 +163,11 @@ static void handle_interrupt(CPUXtensaState *env)
{
int level = env->pending_irq_level;
if (level > xtensa_get_cintlevel(env) &&
level <= env->config->nlevel &&
(env->config->level_mask[level] &
env->sregs[INTSET] &
env->sregs[INTENABLE])) {
if ((level > xtensa_get_cintlevel(env) &&
level <= env->config->nlevel &&
(env->config->level_mask[level] &
env->sregs[INTSET] & env->sregs[INTENABLE])) ||
level == env->config->nmi_level) {
CPUState *cs = env_cpu(env);
if (level > 1) {
@ -173,6 +177,9 @@ static void handle_interrupt(CPUXtensaState *env)
(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
env->pc = relocated_vector(env,
env->config->interrupt_vector[level]);
if (level == env->config->nmi_level) {
intclear(env, env->config->inttype_mask[INTTYPE_NMI]);
}
} else {
env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;

356
target/xtensa/fpu_helper.c
View File

@ -33,7 +33,31 @@
#include "exec/exec-all.h"
#include "fpu/softfloat.h"
void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
enum {
XTENSA_FP_I = 0x1,
XTENSA_FP_U = 0x2,
XTENSA_FP_O = 0x4,
XTENSA_FP_Z = 0x8,
XTENSA_FP_V = 0x10,
};
enum {
XTENSA_FCR_FLAGS_SHIFT = 2,
XTENSA_FSR_FLAGS_SHIFT = 7,
};
static const struct {
uint32_t xtensa_fp_flag;
int softfloat_fp_flag;
} xtensa_fp_flag_map[] = {
{ XTENSA_FP_I, float_flag_inexact, },
{ XTENSA_FP_U, float_flag_underflow, },
{ XTENSA_FP_O, float_flag_overflow, },
{ XTENSA_FP_Z, float_flag_divbyzero, },
{ XTENSA_FP_V, float_flag_invalid, },
};
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
{
static const int rounding_mode[] = {
float_round_nearest_even,
@ -46,121 +70,379 @@ void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
}
void HELPER(wur_fpu_fcr)(CPUXtensaState *env, uint32_t v)
{
static const int rounding_mode[] = {
float_round_nearest_even,
float_round_to_zero,
float_round_up,
float_round_down,
};
if (v & 0xfffff000) {
qemu_log_mask(LOG_GUEST_ERROR,
"MBZ field of FCR is written non-zero: %08x\n", v);
}
env->uregs[FCR] = v & 0x0000007f;
set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
}
void HELPER(wur_fpu_fsr)(CPUXtensaState *env, uint32_t v)
{
uint32_t flags = v >> XTENSA_FSR_FLAGS_SHIFT;
int fef = 0;
unsigned i;
if (v & 0xfffff000) {
qemu_log_mask(LOG_GUEST_ERROR,
"MBZ field of FSR is written non-zero: %08x\n", v);
}
env->uregs[FSR] = v & 0x00000f80;
for (i = 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) {
if (flags & xtensa_fp_flag_map[i].xtensa_fp_flag) {
fef |= xtensa_fp_flag_map[i].softfloat_fp_flag;
}
}
set_float_exception_flags(fef, &env->fp_status);
}
uint32_t HELPER(rur_fpu_fsr)(CPUXtensaState *env)
{
uint32_t flags = 0;
int fef = get_float_exception_flags(&env->fp_status);
unsigned i;
for (i = 0; i < ARRAY_SIZE(xtensa_fp_flag_map); ++i) {
if (fef & xtensa_fp_flag_map[i].softfloat_fp_flag) {
flags |= xtensa_fp_flag_map[i].xtensa_fp_flag;
}
}
env->uregs[FSR] = flags << XTENSA_FSR_FLAGS_SHIFT;
return flags << XTENSA_FSR_FLAGS_SHIFT;
}
float64 HELPER(abs_d)(float64 v)
{
return float64_abs(v);
}
float32 HELPER(abs_s)(float32 v)
{
return float32_abs(v);
}
float64 HELPER(neg_d)(float64 v)
{
return float64_chs(v);
}
float32 HELPER(neg_s)(float32 v)
{
return float32_chs(v);
}
float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
float32 HELPER(fpu2k_add_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_add(a, b, &env->fp_status);
}
float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
float32 HELPER(fpu2k_sub_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_sub(a, b, &env->fp_status);
}
float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
float32 HELPER(fpu2k_mul_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_mul(a, b, &env->fp_status);
}
float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
float32 HELPER(fpu2k_madd_s)(CPUXtensaState *env,
float32 a, float32 b, float32 c)
{
return float32_muladd(b, c, a, 0, &env->fp_status);
}
float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
float32 HELPER(fpu2k_msub_s)(CPUXtensaState *env,
float32 a, float32 b, float32 c)
{
return float32_muladd(b, c, a, float_muladd_negate_product,
&env->fp_status);
}
uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
{
float_status fp_status = {0};
set_float_rounding_mode(rounding_mode, &fp_status);
return float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_status);
set_use_first_nan(true, &env->fp_status);
return float64_add(a, b, &env->fp_status);
}
uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
{
float_status fp_status = {0};
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_add(a, b, &env->fp_status);
}
float64 HELPER(sub_d)(CPUXtensaState *env, float64 a, float64 b)
{
set_use_first_nan(true, &env->fp_status);
return float64_sub(a, b, &env->fp_status);
}
float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_sub(a, b, &env->fp_status);
}
float64 HELPER(mul_d)(CPUXtensaState *env, float64 a, float64 b)
{
set_use_first_nan(true, &env->fp_status);
return float64_mul(a, b, &env->fp_status);
}
float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_mul(a, b, &env->fp_status);
}
float64 HELPER(madd_d)(CPUXtensaState *env, float64 a, float64 b, float64 c)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float64_muladd(b, c, a, 0, &env->fp_status);
}
float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_muladd(b, c, a, 0, &env->fp_status);
}
float64 HELPER(msub_d)(CPUXtensaState *env, float64 a, float64 b, float64 c)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float64_muladd(b, c, a, float_muladd_negate_product,
&env->fp_status);
}
float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_muladd(b, c, a, float_muladd_negate_product,
&env->fp_status);
}
float64 HELPER(mkdadj_d)(CPUXtensaState *env, float64 a, float64 b)
{
set_use_first_nan(true, &env->fp_status);
return float64_div(b, a, &env->fp_status);
}
float32 HELPER(mkdadj_s)(CPUXtensaState *env, float32 a, float32 b)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_div(b, a, &env->fp_status);
}
float64 HELPER(mksadj_d)(CPUXtensaState *env, float64 v)
{
set_use_first_nan(true, &env->fp_status);
return float64_sqrt(v, &env->fp_status);
}
float32 HELPER(mksadj_s)(CPUXtensaState *env, float32 v)
{
set_use_first_nan(env->config->use_first_nan, &env->fp_status);
return float32_sqrt(v, &env->fp_status);
}
uint32_t HELPER(ftoi_d)(CPUXtensaState *env, float64 v,
uint32_t rounding_mode, uint32_t scale)
{
float_status fp_status = env->fp_status;
uint32_t res;
set_float_rounding_mode(rounding_mode, &fp_status);
res = float64_to_int32(float64_scalbn(v, scale, &fp_status), &fp_status);
set_float_exception_flags(get_float_exception_flags(&fp_status),
&env->fp_status);
return res;
}
uint32_t HELPER(ftoi_s)(CPUXtensaState *env, float32 v,
uint32_t rounding_mode, uint32_t scale)
{
float_status fp_status = env->fp_status;
uint32_t res;
set_float_rounding_mode(rounding_mode, &fp_status);
res = float32_to_int32(float32_scalbn(v, scale, &fp_status), &fp_status);
set_float_exception_flags(get_float_exception_flags(&fp_status),
&env->fp_status);
return res;
}
uint32_t HELPER(ftoui_d)(CPUXtensaState *env, float64 v,
uint32_t rounding_mode, uint32_t scale)
{
float_status fp_status = env->fp_status;
float64 res;
uint32_t rv;
set_float_rounding_mode(rounding_mode, &fp_status);
res = float64_scalbn(v, scale, &fp_status);
if (float64_is_neg(v) && !float64_is_any_nan(v)) {
set_float_exception_flags(float_flag_invalid, &fp_status);
rv = float64_to_int32(res, &fp_status);
} else {
rv = float64_to_uint32(res, &fp_status);
}
set_float_exception_flags(get_float_exception_flags(&fp_status),
&env->fp_status);
return rv;
}
uint32_t HELPER(ftoui_s)(CPUXtensaState *env, float32 v,
uint32_t rounding_mode, uint32_t scale)
{
float_status fp_status = env->fp_status;
float32 res;
uint32_t rv;
set_float_rounding_mode(rounding_mode, &fp_status);
res = float32_scalbn(v, scale, &fp_status);
if (float32_is_neg(v) && !float32_is_any_nan(v)) {
return float32_to_int32(res, &fp_status);
rv = float32_to_int32(res, &fp_status);
if (rv) {
set_float_exception_flags(float_flag_invalid, &fp_status);
}
} else {
return float32_to_uint32(res, &fp_status);
rv = float32_to_uint32(res, &fp_status);
}
set_float_exception_flags(get_float_exception_flags(&fp_status),
&env->fp_status);
return rv;
}
float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
float64 HELPER(itof_d)(CPUXtensaState *env, uint32_t v, uint32_t scale)
{
return float64_scalbn(int32_to_float64(v, &env->fp_status),
(int32_t)scale, &env->fp_status);
}
float32 HELPER(itof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale)
{
return float32_scalbn(int32_to_float32(v, &env->fp_status),
(int32_t)scale, &env->fp_status);
}
float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
float64 HELPER(uitof_d)(CPUXtensaState *env, uint32_t v, uint32_t scale)
{
return float64_scalbn(uint32_to_float64(v, &env->fp_status),
(int32_t)scale, &env->fp_status);
}
float32 HELPER(uitof_s)(CPUXtensaState *env, uint32_t v, uint32_t scale)
{
return float32_scalbn(uint32_to_float32(v, &env->fp_status),
(int32_t)scale, &env->fp_status);
}
static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
float64 HELPER(cvtd_s)(CPUXtensaState *env, float32 v)
{
if (v) {
env->sregs[BR] |= br;
} else {
env->sregs[BR] &= ~br;
}
return float32_to_float64(v, &env->fp_status);
}
void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
float32 HELPER(cvts_d)(CPUXtensaState *env, float64 v)
{
set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
return float64_to_float32(v, &env->fp_status);
}
void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
uint32_t HELPER(un_d)(CPUXtensaState *env, float64 a, float64 b)
{
set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
return float64_unordered_quiet(a, b, &env->fp_status);
}
void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
uint32_t HELPER(un_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_unordered_quiet(a, b, &env->fp_status);
}
uint32_t HELPER(oeq_d)(CPUXtensaState *env, float64 a, float64 b)
{
return float64_eq_quiet(a, b, &env->fp_status);
}
uint32_t HELPER(oeq_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_eq_quiet(a, b, &env->fp_status);
}
uint32_t HELPER(ueq_d)(CPUXtensaState *env, float64 a, float64 b)
{
FloatRelation v = float64_compare_quiet(a, b, &env->fp_status);
return v == float_relation_equal ||
v == float_relation_unordered;
}
uint32_t HELPER(ueq_s)(CPUXtensaState *env, float32 a, float32 b)
{
FloatRelation v = float32_compare_quiet(a, b, &env->fp_status);
set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
return v == float_relation_equal ||
v == float_relation_unordered;
}
void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
uint32_t HELPER(olt_d)(CPUXtensaState *env, float64 a, float64 b)
{
set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
return float64_lt(a, b, &env->fp_status);
}
void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
uint32_t HELPER(olt_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_lt(a, b, &env->fp_status);
}
uint32_t HELPER(ult_d)(CPUXtensaState *env, float64 a, float64 b)
{
FloatRelation v = float64_compare_quiet(a, b, &env->fp_status);
return v == float_relation_less ||
v == float_relation_unordered;
}
uint32_t HELPER(ult_s)(CPUXtensaState *env, float32 a, float32 b)
{
FloatRelation v = float32_compare_quiet(a, b, &env->fp_status);
set_br(env, v == float_relation_less || v == float_relation_unordered, br);
return v == float_relation_less ||
v == float_relation_unordered;
}
void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
uint32_t HELPER(ole_d)(CPUXtensaState *env, float64 a, float64 b)
{
set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
return float64_le(a, b, &env->fp_status);
}
void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
uint32_t HELPER(ole_s)(CPUXtensaState *env, float32 a, float32 b)
{
return float32_le(a, b, &env->fp_status);
}
uint32_t HELPER(ule_d)(CPUXtensaState *env, float64 a, float64 b)
{
FloatRelation v = float64_compare_quiet(a, b, &env->fp_status);
return v != float_relation_greater;
}
uint32_t HELPER(ule_s)(CPUXtensaState *env, float32 a, float32 b)
{
FloatRelation v = float32_compare_quiet(a, b, &env->fp_status);
set_br(env, v != float_relation_greater, br);
return v != float_relation_greater;
}

4
target/xtensa/helper.c
View File

@ -133,8 +133,10 @@ static void init_libisa(XtensaConfig *config)
config->regfile = g_new(void **, regfiles);
for (i = 0; i < regfiles; ++i) {
const char *name = xtensa_regfile_name(config->isa, i);
int entries = xtensa_regfile_num_entries(config->isa, i);
int bits = xtensa_regfile_num_bits(config->isa, i);
config->regfile[i] = xtensa_get_regfile_by_name(name);
config->regfile[i] = xtensa_get_regfile_by_name(name, entries, bits);
#ifdef DEBUG
if (config->regfile[i] == NULL) {
fprintf(stderr, "regfile '%s' not found for %s\n",

68
target/xtensa/helper.h
View File

@ -46,26 +46,60 @@ DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32)
DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32)
#endif
DEF_HELPER_2(wur_fcr, void, env, i32)
DEF_HELPER_2(wur_fpu2k_fcr, void, env, i32)
DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_1(neg_s, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_3(add_s, f32, env, f32, f32)
DEF_HELPER_3(sub_s, f32, env, f32, f32)
DEF_HELPER_3(mul_s, f32, env, f32, f32)
DEF_HELPER_4(madd_s, f32, env, f32, f32, f32)
DEF_HELPER_4(msub_s, f32, env, f32, f32, f32)
DEF_HELPER_FLAGS_3(ftoi, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32)
DEF_HELPER_FLAGS_3(ftoui, TCG_CALL_NO_RWG_SE, i32, f32, i32, i32)
DEF_HELPER_3(itof, f32, env, i32, i32)
DEF_HELPER_3(uitof, f32, env, i32, i32)
DEF_HELPER_3(fpu2k_add_s, f32, env, f32, f32)
DEF_HELPER_3(fpu2k_sub_s, f32, env, f32, f32)
DEF_HELPER_3(fpu2k_mul_s, f32, env, f32, f32)
DEF_HELPER_4(fpu2k_madd_s, f32, env, f32, f32, f32)
DEF_HELPER_4(fpu2k_msub_s, f32, env, f32, f32, f32)
DEF_HELPER_4(ftoi_s, i32, env, f32, i32, i32)
DEF_HELPER_4(ftoui_s, i32, env, f32, i32, i32)
DEF_HELPER_3(itof_s, f32, env, i32, i32)
DEF_HELPER_3(uitof_s, f32, env, i32, i32)
DEF_HELPER_2(cvtd_s, f64, env, f32)
DEF_HELPER_4(un_s, void, env, i32, f32, f32)
DEF_HELPER_4(oeq_s, void, env, i32, f32, f32)
DEF_HELPER_4(ueq_s, void, env, i32, f32, f32)
DEF_HELPER_4(olt_s, void, env, i32, f32, f32)
DEF_HELPER_4(ult_s, void, env, i32, f32, f32)
DEF_HELPER_4(ole_s, void, env, i32, f32, f32)
DEF_HELPER_4(ule_s, void, env, i32, f32, f32)
DEF_HELPER_3(un_s, i32, env, f32, f32)
DEF_HELPER_3(oeq_s, i32, env, f32, f32)
DEF_HELPER_3(ueq_s, i32, env, f32, f32)
DEF_HELPER_3(olt_s, i32, env, f32, f32)
DEF_HELPER_3(ult_s, i32, env, f32, f32)
DEF_HELPER_3(ole_s, i32, env, f32, f32)
DEF_HELPER_3(ule_s, i32, env, f32, f32)
DEF_HELPER_2(wur_fpu_fcr, void, env, i32)
DEF_HELPER_1(rur_fpu_fsr, i32, env)
DEF_HELPER_2(wur_fpu_fsr, void, env, i32)
DEF_HELPER_FLAGS_1(abs_d, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_1(neg_d, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_3(add_d, f64, env, f64, f64)
DEF_HELPER_3(add_s, f32, env, f32, f32)
DEF_HELPER_3(sub_d, f64, env, f64, f64)
DEF_HELPER_3(sub_s, f32, env, f32, f32)
DEF_HELPER_3(mul_d, f64, env, f64, f64)
DEF_HELPER_3(mul_s, f32, env, f32, f32)
DEF_HELPER_4(madd_d, f64, env, f64, f64, f64)
DEF_HELPER_4(madd_s, f32, env, f32, f32, f32)
DEF_HELPER_4(msub_d, f64, env, f64, f64, f64)
DEF_HELPER_4(msub_s, f32, env, f32, f32, f32)
DEF_HELPER_3(mkdadj_d, f64, env, f64, f64)
DEF_HELPER_3(mkdadj_s, f32, env, f32, f32)
DEF_HELPER_2(mksadj_d, f64, env, f64)
DEF_HELPER_2(mksadj_s, f32, env, f32)
DEF_HELPER_4(ftoi_d, i32, env, f64, i32, i32)
DEF_HELPER_4(ftoui_d, i32, env, f64, i32, i32)
DEF_HELPER_3(itof_d, f64, env, i32, i32)
DEF_HELPER_3(uitof_d, f64, env, i32, i32)
DEF_HELPER_2(cvts_d, f32, env, f64)
DEF_HELPER_3(un_d, i32, env, f64, f64)
DEF_HELPER_3(oeq_d, i32, env, f64, f64)
DEF_HELPER_3(ueq_d, i32, env, f64, f64)
DEF_HELPER_3(olt_d, i32, env, f64, f64)
DEF_HELPER_3(ult_d, i32, env, f64, f64)
DEF_HELPER_3(ole_d, i32, env, f64, f64)
DEF_HELPER_3(ule_d, i32, env, f64, f64)
DEF_HELPER_2(rer, i32, env, i32)
DEF_HELPER_3(wer, void, env, i32, i32)

2
target/xtensa/meson.build
View File

@ -3,6 +3,8 @@ xtensa_ss.add(files(
'core-dc232b.c',
'core-dc233c.c',
'core-de212.c',
'core-de233_fpu.c',
'core-dsp3400.c',
'core-fsf.c',
'core-sample_controller.c',
'core-test_kc705_be.c',

30
target/xtensa/overlay_tool.h
View File

@ -39,6 +39,26 @@
#define XCHAL_HAVE_DEPBITS 0
#endif
#ifndef XCHAL_HAVE_DFP
#define XCHAL_HAVE_DFP 0
#endif
#ifndef XCHAL_HAVE_DFPU_SINGLE_ONLY
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0
#endif
#ifndef XCHAL_HAVE_DFPU_SINGLE_DOUBLE
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE XCHAL_HAVE_DFP
#endif
/*
* We need to know the type of FP unit, not only its precision.
* Unfortunately XCHAL macros don't tell this explicitly.
*/
#define XCHAL_HAVE_DFPU (XCHAL_HAVE_DFP || \
XCHAL_HAVE_DFPU_SINGLE_ONLY || \
XCHAL_HAVE_DFPU_SINGLE_DOUBLE)
#ifndef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#endif
@ -99,6 +119,9 @@
XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
XCHAL_OPTION(XCHAL_HAVE_DFPU, XTENSA_OPTION_DFP_COPROCESSOR) | \
XCHAL_OPTION(XCHAL_HAVE_DFPU_SINGLE_ONLY, \
XTENSA_OPTION_DFPU_SINGLE_ONLY) | \
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
@ -216,6 +239,9 @@
#define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR
#define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR
#ifndef XCHAL_NMILEVEL
#define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS + 1)
#endif
#define INTERRUPT(i) { \
.level = XCHAL_INT ## i ## _LEVEL, \
@ -305,7 +331,8 @@
#define INTERRUPTS_SECTION \
.ninterrupt = XCHAL_NUM_INTERRUPTS, \
.nlevel = XCHAL_NUM_INTLEVELS, \
.nlevel = XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI, \
.nmi_level = XCHAL_NMILEVEL, \
.interrupt_vector = INTERRUPT_VECTORS, \
.level_mask = LEVEL_MASKS, \
.inttype_mask = INTTYPE_MASKS, \
@ -511,6 +538,7 @@
.ndepc = (XCHAL_XEA_VERSION >= 2), \
.inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
.max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
.use_first_nan = !XCHAL_HAVE_DFPU, \
EXCEPTIONS_SECTION, \
INTERRUPTS_SECTION, \
TLB_SECTION, \

1967
target/xtensa/translate.c
View File

File diff suppressed because it is too large Load Diff

142
tests/tcg/xtensa/fpu.h Normal file
View File

@ -0,0 +1,142 @@
#if XCHAL_HAVE_DFP || XCHAL_HAVE_FP_DIV
#define DFPU 1
#else
#define DFPU 0
#endif
#define FCR_RM_NEAREST 0
#define FCR_RM_TRUNC 1
#define FCR_RM_CEIL 2
#define FCR_RM_FLOOR 3
#define FSR__ 0x00000000
#define FSR_I 0x00000080
#define FSR_U 0x00000100
#define FSR_O 0x00000200
#define FSR_Z 0x00000400
#define FSR_V 0x00000800
#define FSR_UI (FSR_U | FSR_I)
#define FSR_OI (FSR_O | FSR_I)
#define F32_0 0x00000000
#define F32_0_5 0x3f000000
#define F32_1 0x3f800000
#define F32_MAX 0x7f7fffff
#define F32_PINF 0x7f800000
#define F32_NINF 0xff800000
#define F32_DNAN 0x7fc00000
#define F32_SNAN(v) (0x7f800000 | (v))
#define F32_QNAN(v) (0x7fc00000 | (v))
#define F32_MINUS 0x80000000
#define F64_0 0x0000000000000000
#define F64_MIN_NORM 0x0010000000000000
#define F64_1 0x3ff0000000000000
#define F64_MAX_2 0x7fe0000000000000
#define F64_MAX 0x7fefffffffffffff
#define F64_PINF 0x7ff0000000000000
#define F64_NINF 0xfff0000000000000
#define F64_DNAN 0x7ff8000000000000
#define F64_SNAN(v) (0x7ff0000000000000 | (v))
#define F64_QNAN(v) (0x7ff8000000000000 | (v))
#define F64_MINUS 0x8000000000000000
.macro test_op1_rm op, fr0, fr1, v0, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
\op \fr1, \fr0
check_res \fr1, \r, \sr
.endm
.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
movfp \fr1, \v1
\op \fr2, \fr0, \fr1
check_res \fr2, \r, \sr
.endm
.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
movfp \fr1, \v1
movfp \fr2, \v2
\op \fr0, \fr1, \fr2
check_res \fr3, \r, \sr
.endm
.macro test_op1_ex op, fr0, fr1, v0, rm, r, sr
movi a2, \rm
wur a2, fcr
test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
movi a2, (\rm) | 0x7c
wur a2, fcr
test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
.endm
.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr
movi a2, \rm
wur a2, fcr
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
movi a2, (\rm) | 0x7c
wur a2, fcr
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
.endm
.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r, sr
movi a2, \rm
wur a2, fcr
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
movi a2, (\rm) | 0x7c
wur a2, fcr
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
.endm
.macro test_op1 op, fr0, fr1, v0, r0, r1, r2, r3, sr0, sr1, sr2, sr3
test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0
test_op1_ex \op, \fr0, \fr1, \v0, 1, \r1, \sr1
test_op1_ex \op, \fr0, \fr1, \v0, 2, \r2, \sr2
test_op1_ex \op, \fr0, \fr1, \v0, 3, \r3, \sr3
.endm
.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3, sr0, sr1, sr2, sr3
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0, \sr0
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1, \sr1
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2, \sr2
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3, \sr3
.endm
.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3, sr0, sr1, sr2, sr3
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0, \sr0
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1, \sr1
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2, \sr2
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3, \sr3
.endm
.macro test_op2_cpe op
set_vector kernel, 2f
movi a2, 0
wsr a2, cpenable
1:
\op f2, f0, f1
test_fail
2:
rsr a2, excvaddr
movi a3, 1b
assert eq, a2, a3
rsr a2, exccause
movi a3, 32
assert eq, a2, a3
set_vector kernel, 0
movi a2, 1
wsr a2, cpenable
.endm

10
tests/tcg/xtensa/macros.inc
View File

@ -3,7 +3,7 @@
.macro test_suite name
.data
status: .word result
result: .space 256
result: .space 1024
.text
.global main
.align 4
@ -25,9 +25,9 @@ main:
movi a3, 0
beqz a2, 2f
1:
l8ui a1, a0, 0
l32i a1, a0, 0
or a3, a3, a1
addi a0, a0, 1
addi a0, a0, 4
addi a2, a2, -1
bnez a2, 1b
2:
@ -65,7 +65,7 @@ test_\name:
reset_ps
movi a2, status
l32i a3, a2, 0
addi a3, a3, 1
addi a3, a3, 4
s32i a3, a2, 0
.endm
@ -78,7 +78,7 @@ test_\name:
movi a2, status
l32i a2, a2, 0
movi a3, 1
s8i a3, a2, 0
s32i a3, a2, 0
#ifdef DEBUG
print failed
#endif

162
tests/tcg/xtensa/test_dfp0_arith.S Normal file
View File

@ -0,0 +1,162 @@
#include "macros.inc"
#include "fpu.h"
test_suite fp0_arith
#if XCHAL_HAVE_DFP
.macro movfp fr, v
movi a2, ((\v) >> 32) & 0xffffffff
movi a3, ((\v) & 0xffffffff)
wfrd \fr, a2, a3
.endm
.macro check_res fr, r, sr
rfrd a2, \fr
dump a2
movi a3, ((\r) >> 32) & 0xffffffff
assert eq, a2, a3
rfr a2, \fr
dump a2
movi a3, ((\r) & 0xffffffff)
assert eq, a2, a3
rur a2, fsr
movi a3, \sr
assert eq, a2, a3
.endm
test add_d
movi a2, 1
wsr a2, cpenable
/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
test_op2 add.d, f6, f7, f8, F64_MAX, F64_MAX, \
F64_PINF, F64_MAX, F64_PINF, F64_MAX, \
FSR_OI, FSR_OI, FSR_OI, FSR_OI
test_end
test add_d_inf
/* 1 + +inf = +inf */
test_op2 add.d, f6, f7, f8, F64_1, F64_PINF, \
F64_PINF, F64_PINF, F64_PINF, F64_PINF, \
FSR__, FSR__, FSR__, FSR__
/* +inf + -inf = default NaN */
test_op2 add.d, f0, f1, f2, F64_PINF, F64_NINF, \
F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
test add_d_nan_dfpu
/* 1 + QNaN = QNaN */
test_op2 add.d, f9, f10, f11, F64_1, F64_QNAN(1), \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
/* 1 + SNaN = QNaN */
test_op2 add.d, f12, f13, f14, F64_1, F64_SNAN(1), \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
/* SNaN1 + SNaN2 = QNaN2 */
test_op2 add.d, f15, f0, f1, F64_SNAN(1), F64_SNAN(2), \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
/* QNaN1 + SNaN2 = QNaN2 */
test_op2 add.d, f5, f6, f7, F64_QNAN(1), F64_SNAN(2), \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
/* SNaN1 + QNaN2 = QNaN2 */
test_op2 add.d, f8, f9, f10, F64_SNAN(1), F64_QNAN(2), \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
test sub_d
/* norm - norm = denorm */
test_op2 sub.d, f6, f7, f8, F64_MIN_NORM | 1, F64_MIN_NORM, \
0x00000001, 0x00000001, 0x00000001, 0x00000001, \
FSR__, FSR__, FSR__, FSR__
test_end
test mul_d
test_op2 mul.d, f0, f1, f2, F64_1 | 1, F64_1 | 1, \
F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \
FSR_I, FSR_I, FSR_I, FSR_I
/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
test_op2 mul.d, f6, f7, f8, F64_MAX_2, F64_MAX_2, \
F64_PINF, F64_MAX, F64_PINF, F64_MAX, \
FSR_OI, FSR_OI, FSR_OI, FSR_OI
/* min norm * min norm = 0/denorm */
test_op2 mul.d, f6, f7, f8, F64_MIN_NORM, F64_MIN_NORM, \
F64_0, F64_0, 0x00000001, F64_0, \
FSR_UI, FSR_UI, FSR_UI, FSR_UI
/* inf * 0 = default NaN */
test_op2 mul.d, f6, f7, f8, F64_PINF, F64_0, \
F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
test madd_d
test_op3 madd.d, f0, f1, f2, f0, F64_0, F64_1 | 1, F64_1 | 1, \
F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \
FSR_I, FSR_I, FSR_I, FSR_I
test_end
test madd_d_precision
test_op3 madd.d, f0, f1, f2, f0, \
F64_MINUS | F64_1 | 2, F64_1 | 1, F64_1 | 1, \
0x3970000000000000, 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, \
FSR__, FSR__, FSR__, FSR__
test_end
test madd_d_nan_dfpu
/* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */
test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_1, \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_1, \
F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_1, F64_QNAN(3), \
F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_1, \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_QNAN(3), \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_QNAN(3), \
F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_QNAN(3), \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
/* inf * 0 = default NaN */
test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_PINF, F64_0, \
F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
FSR_V, FSR_V, FSR_V, FSR_V
/* inf * 0 + SNaN1 = QNaN1 */
test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_PINF, F64_0, \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
/* inf * 0 + QNaN1 = QNaN1 */
test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_PINF, F64_0, \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
/* madd/msub SNaN turns to QNaN and sets Invalid flag */
test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_1, F64_1, \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_SNAN(2), F64_1, \
F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
#endif
test_suite_end

282
tests/tcg/xtensa/test_fp0_arith.S
View File

@ -1,4 +1,5 @@
#include "macros.inc"
#include "fpu.h"
test_suite fp0_arith
@ -9,84 +10,18 @@ test_suite fp0_arith
wfr \fr, a2
.endm
.macro check_res fr, r
.macro check_res fr, r, sr
rfr a2, \fr
dump a2
movi a3, \r
assert eq, a2, a3
rur a2, fsr
#if DFPU
movi a3, \sr
assert eq, a2, a3
#else
assert eqi, a2, 0
.endm
.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
movfp \fr1, \v1
\op \fr2, \fr0, \fr1
check_res \fr2, \r
.endm
.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
movfp \fr1, \v1
movfp \fr2, \v2
\op \fr0, \fr1, \fr2
check_res \fr3, \r
.endm
.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r
movi a2, \rm
wur a2, fcr
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
movi a2, (\rm) | 0x7c
wur a2, fcr
test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
.endm
.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r
movi a2, \rm
wur a2, fcr
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
movi a2, (\rm) | 0x7c
wur a2, fcr
test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
.endm
.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2
test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3
.endm
.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2
test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3
.endm
.macro test_op2_cpe op
set_vector kernel, 2f
movi a2, 0
wsr a2, cpenable
1:
\op f2, f0, f1
test_fail
2:
rsr a2, excvaddr
movi a3, 1b
assert eq, a2, a3
rsr a2, exccause
movi a3, 32
assert eq, a2, a3
set_vector kernel, 0
movi a2, 1
wsr a2, cpenable
#endif
.endm
test add_s
@ -94,78 +29,231 @@ test add_s
wsr a2, cpenable
test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001
0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001, \
FSR_I, FSR_I, FSR_I, FSR_I
test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002
0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002, \
FSR_I, FSR_I, FSR_I, FSR_I
/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
FSR_OI, FSR_OI, FSR_OI, FSR_OI
test_end
test add_s_inf
/* 1 + +inf = +inf */
test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000
0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, \
FSR__, FSR__, FSR__, FSR__
/* +inf + -inf = default NaN */
test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
test add_s_nan
/* 1 + NaN = NaN */
#if DFPU
test add_s_nan_dfpu
/* 1 + QNaN = QNaN */
test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
FSR__, FSR__, FSR__, FSR__
/* 1 + SNaN = QNaN */
test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
FSR_V, FSR_V, FSR_V, FSR_V
/* NaN1 + NaN2 = NaN1 */
/* SNaN1 + SNaN2 = QNaN2 */
test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
FSR_V, FSR_V, FSR_V, FSR_V
test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
FSR_V, FSR_V, FSR_V, FSR_V
/* QNaN1 + SNaN2 = QNaN2 */
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
FSR_V, FSR_V, FSR_V, FSR_V
/* SNaN1 + QNaN2 = QNaN2 */
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
#else
test add_s_nan_fpu2k
/* 1 + QNaN = QNaN */
test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
FSR__, FSR__, FSR__, FSR__
/* 1 + SNaN = SNaN */
test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
FSR__, FSR__, FSR__, FSR__
/* SNaN1 + SNaN2 = SNaN1 */
test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
FSR__, FSR__, FSR__, FSR__
test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
FSR__, FSR__, FSR__, FSR__
/* QNaN1 + SNaN2 = QNaN1 */
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
FSR__, FSR__, FSR__, FSR__
/* SNaN1 + QNaN2 = SNaN1 */
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
FSR__, FSR__, FSR__, FSR__
test_end
#endif
test sub_s
test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000
0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000, \
FSR_I, FSR_I, FSR_I, FSR_I
test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001
0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001, \
FSR_I, FSR_I, FSR_I, FSR_I
/* norm - norm = denorm */
test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \
0x00000001, 0x00000001, 0x00000001, 0x00000001
0x00000001, 0x00000001, 0x00000001, 0x00000001, \
FSR__, FSR__, FSR__, FSR__
test_end
test mul_s
test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
FSR_I, FSR_I, FSR_I, FSR_I
/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
FSR_OI, FSR_OI, FSR_OI, FSR_OI
/* min norm * min norm = 0/denorm */
test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
0x00000000, 0x00000000, 0x00000001, 0x00000000
0x00000000, 0x00000000, 0x00000001, 0x00000000, \
FSR_UI, FSR_UI, FSR_UI, FSR_UI
/* inf * 0 = default NaN */
test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
test madd_s
test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
FSR_I, FSR_I, FSR_I, FSR_I
test_end
test madd_s_precision
test_op3 madd.s, f0, f1, f2, f0, 0xbf800002, 0x3f800001, 0x3f800001, \
0x28800000, 0x28800000, 0x28800000, 0x28800000, \
FSR__, FSR__, FSR__, FSR__
test_end
#if DFPU
test madd_s_nan_dfpu
/* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
/* inf * 0 = default NaN */
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
FSR_V, FSR_V, FSR_V, FSR_V
/* inf * 0 + SNaN1 = QNaN1 */
test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
/* inf * 0 + QNaN1 = QNaN1 */
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
/* madd/msub SNaN turns to QNaN and sets Invalid flag */
test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
#else
test madd_s_nan_fpu2k
/* FPU2000 madd/msub NaN1, NaN2, NaN3 priority: NaN2, NaN3, NaN1 */
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
FSR__, FSR__, FSR__, FSR__
/* inf * 0 = default NaN */
test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
FSR__, FSR__, FSR__, FSR__
/* inf * 0 + SNaN1 = SNaN1 */
test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
FSR__, FSR__, FSR__, FSR__
/* inf * 0 + QNaN1 = QNaN1 */
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
FSR__, FSR__, FSR__, FSR__
/* madd/msub SNaN is preserved */
test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
FSR__, FSR__, FSR__, FSR__
test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), \
FSR__, FSR__, FSR__, FSR__
test_end
#endif
test msub_s
test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001
0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \
FSR_I, FSR_I, FSR_I, FSR_I
test_end
#endif

299
tests/tcg/xtensa/test_fp0_conv.S
View File

@ -1,4 +1,5 @@
#include "macros.inc"
#include "fpu.h"
test_suite fp0_conv
@ -9,7 +10,7 @@ test_suite fp0_conv
wfr \fr, a2
.endm
.macro test_ftoi_ex op, r0, fr0, v, c, r
.macro test_ftoi_ex op, r0, fr0, v, c, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v
@ -18,20 +19,25 @@ test_suite fp0_conv
movi a3, \r
assert eq, \r0, a3
rur a2, fsr
#if DFPU
movi a3, \sr
assert eq, a2, a3
#else
assert eqi, a2, 0
#endif
.endm
.macro test_ftoi op, r0, fr0, v, c, r
.macro test_ftoi op, r0, fr0, v, c, r, sr
movi a2, 0
wur a2, fcr
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr
movi a2, 0x7c
wur a2, fcr
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r
test_ftoi_ex \op, \r0, \fr0, \v, \c, \r, \sr
.endm
.macro test_itof_ex op, fr0, ar0, v, c, r
.macro test_itof_ex op, fr0, ar0, v, c, r, sr
movi a2, 0
wur a2, fsr
movi \ar0, \v
@ -42,23 +48,28 @@ test_suite fp0_conv
movi a3, \r
assert eq, a2, a3
rur a2, fsr
#if DFPU
movi a3, \sr
assert eq, a2, a3
#else
assert eqi, a2, 0
#endif
.endm
.macro test_itof_rm op, fr0, ar0, v, c, rm, r
.macro test_itof_rm op, fr0, ar0, v, c, rm, r, sr
movi a2, \rm
wur a2, fcr
test_itof_ex \op, \fr0, \ar0, \v, \c, \r
test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr
movi a2, (\rm) | 0x7c
wur a2, fcr
test_itof_ex \op, \fr0, \ar0, \v, \c, \r
test_itof_ex \op, \fr0, \ar0, \v, \c, \r, \sr
.endm
.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3
test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0
test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1
test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2
test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3
.macro test_itof op, fr0, ar0, v, c, r0, r1, r2, r3, sr
test_itof_rm \op, \fr0, \ar0, \v, \c, 0, \r0, \sr
test_itof_rm \op, \fr0, \ar0, \v, \c, 1, \r1, \sr
test_itof_rm \op, \fr0, \ar0, \v, \c, 2, \r2, \sr
test_itof_rm \op, \fr0, \ar0, \v, \c, 3, \r3, \sr
.endm
test round_s
@ -66,237 +77,237 @@ test round_s
wsr a2, cpenable
/* NaN */
test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
test_ftoi round.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000
test_ftoi round.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080
test_ftoi round.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
test_ftoi round.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
test_ftoi round.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
test_ftoi round.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi round.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi round.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
test_ftoi round.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
test_ftoi round.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
test_ftoi round.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */
test_ftoi round.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
test_ftoi round.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
test_ftoi round.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */
test_ftoi round.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
test_ftoi round.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi round.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
test_ftoi round.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi round.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
test_ftoi round.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
test_ftoi round.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */
test_ftoi round.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
test_ftoi round.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
test_ftoi round.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */
test_ftoi round.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff
test_ftoi round.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
test_ftoi round.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
test_ftoi round.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_ftoi round.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
test_ftoi round.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test trunc_s
/* NaN */
test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
test_ftoi trunc.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000
test_ftoi trunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080
test_ftoi trunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
test_ftoi trunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
test_ftoi trunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
test_ftoi trunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
test_ftoi trunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */
test_ftoi trunc.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
test_ftoi trunc.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
test_ftoi trunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */
test_ftoi trunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
test_ftoi trunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
test_ftoi trunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */
test_ftoi trunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
test_ftoi trunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
test_ftoi trunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */
test_ftoi trunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
test_ftoi trunc.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
test_ftoi trunc.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_ftoi trunc.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
test_ftoi trunc.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test floor_s
/* NaN */
test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
test_ftoi floor.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000
test_ftoi floor.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080
test_ftoi floor.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
test_ftoi floor.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
test_ftoi floor.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3 /* -1.25 * 2 */
test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2 /* -1.5 */
test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1 /* -0.75 */
test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1 /* -0.5 */
test_ftoi floor.s, a2, f0, 0xbfa00000, 1, -3, FSR_I /* -1.25 * 2 */
test_ftoi floor.s, a2, f0, 0xbfc00000, 0, -2, FSR_I /* -1.5 */
test_ftoi floor.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
test_ftoi floor.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
test_ftoi floor.s, a2, f0, 0xbf400000, 0, -1, FSR_I /* -0.75 */
test_ftoi floor.s, a2, f0, 0xbf000000, 0, -1, FSR_I /* -0.5 */
/* positive */
test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
test_ftoi floor.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
test_ftoi floor.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */
test_ftoi floor.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
test_ftoi floor.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
test_ftoi floor.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */
test_ftoi floor.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff
test_ftoi floor.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
test_ftoi floor.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
test_ftoi floor.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_ftoi floor.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
test_ftoi floor.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test ceil_s
/* NaN */
test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0xffc00001, 0, 0x7fffffff, FSR_V
test_ftoi ceil.s, a2, f0, 0xff800001, 0, 0x7fffffff, FSR_V
/* -inf */
test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000
test_ftoi ceil.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080
test_ftoi ceil.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
test_ftoi ceil.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR__
test_ftoi ceil.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR__
/* negative */
test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
test_ftoi ceil.s, a2, f0, 0xbfa00000, 1, -2, FSR_I /* -1.25 * 2 */
test_ftoi ceil.s, a2, f0, 0xbfc00000, 0, -1, FSR_I /* -1.5 */
test_ftoi ceil.s, a2, f0, 0xbf800000, 1, -2, FSR__ /* -1 * 2 */
test_ftoi ceil.s, a2, f0, 0xbf800000, 0, -1, FSR__ /* -1 */
test_ftoi ceil.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */
test_ftoi ceil.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1 /* 0.5 */
test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1 /* 0.75 */
test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2 /* 1.5 */
test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3 /* 1.25 * 2 */
test_ftoi ceil.s, a2, f0, 0x3f000000, 0, 1, FSR_I /* 0.5 */
test_ftoi ceil.s, a2, f0, 0x3f400000, 0, 1, FSR_I /* 0.75 */
test_ftoi ceil.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
test_ftoi ceil.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
test_ftoi ceil.s, a2, f0, 0x3fc00000, 0, 2, FSR_I /* 1.5 */
test_ftoi ceil.s, a2, f0, 0x3fa00000, 1, 3, FSR_I /* 1.25 * 2 */
/* positive overflow */
test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
test_ftoi ceil.s, a2, f0, 0x4f000000, 0, 0x7fffffff, FSR_V
test_ftoi ceil.s, a2, f0, 0x4effffff, 1, 0x7fffffff, FSR_V
/* +inf */
test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0x7f800000, 0, 0x7fffffff, FSR_V
/* NaN */
test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff
test_ftoi ceil.s, a2, f0, 0x7f800001, 0, 0x7fffffff, FSR_V
test_ftoi ceil.s, a2, f0, 0x7fc00000, 0, 0x7fffffff, FSR_V
test_end
test utrunc_s
/* NaN */
test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0xffc00001, 0, 0xffffffff, FSR_V
test_ftoi utrunc.s, a2, f0, 0xff800001, 0, 0xffffffff, FSR_V
/* -inf */
test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000
test_ftoi utrunc.s, a2, f0, 0xff800000, 0, 0x80000000, FSR_V
/* negative overflow */
test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000
test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000
test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080
test_ftoi utrunc.s, a2, f0, 0xceffffff, 1, 0x80000000, FSR_V
test_ftoi utrunc.s, a2, f0, 0xcf000000, 0, 0x80000000, FSR_V
test_ftoi utrunc.s, a2, f0, 0xceffffff, 0, 0x80000080, FSR_V
/* negative */
test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2 /* -1.25 * 2 */
test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1 /* -1.5 */
test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2 /* -1 * 2 */
test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1 /* -1 */
test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0 /* -0.75 */
test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0 /* -0.5 */
test_ftoi utrunc.s, a2, f0, 0xbfa00000, 1, -2, FSR_V /* -1.25 * 2 */
test_ftoi utrunc.s, a2, f0, 0xbfc00000, 0, -1, FSR_V /* -1.5 */
test_ftoi utrunc.s, a2, f0, 0xbf800000, 1, -2, FSR_V /* -1 * 2 */
test_ftoi utrunc.s, a2, f0, 0xbf800000, 0, -1, FSR_V /* -1 */
test_ftoi utrunc.s, a2, f0, 0xbf400000, 0, 0, FSR_I /* -0.75 */
test_ftoi utrunc.s, a2, f0, 0xbf000000, 0, 0, FSR_I /* -0.5 */
/* positive */
test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0 /* 0.5 */
test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0 /* 0.75 */
test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1 /* 1 */
test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2 /* 1 * 2 */
test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1 /* 1.5 */
test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2 /* 1.25 * 2 */
test_ftoi utrunc.s, a2, f0, 0x3f000000, 0, 0, FSR_I /* 0.5 */
test_ftoi utrunc.s, a2, f0, 0x3f400000, 0, 0, FSR_I /* 0.75 */
test_ftoi utrunc.s, a2, f0, 0x3f800000, 0, 1, FSR__ /* 1 */
test_ftoi utrunc.s, a2, f0, 0x3f800000, 1, 2, FSR__ /* 1 * 2 */
test_ftoi utrunc.s, a2, f0, 0x3fc00000, 0, 1, FSR_I /* 1.5 */
test_ftoi utrunc.s, a2, f0, 0x3fa00000, 1, 2, FSR_I /* 1.25 * 2 */
/* positive overflow */
test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80
test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000
test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00
test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0x4effffff, 0, 0x7fffff80, FSR__
test_ftoi utrunc.s, a2, f0, 0x4f000000, 0, 0x80000000, FSR__
test_ftoi utrunc.s, a2, f0, 0x4effffff, 1, 0xffffff00, FSR__
test_ftoi utrunc.s, a2, f0, 0x4f800000, 1, 0xffffffff, FSR_V
/* +inf */
test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0x7f800000, 0, 0xffffffff, FSR_V
/* NaN */
test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff
test_ftoi utrunc.s, a2, f0, 0x7f800001, 0, 0xffffffff, FSR_V
test_ftoi utrunc.s, a2, f0, 0x7fc00000, 0, 0xffffffff, FSR_V
test_end
test float_s
test_itof float.s, f0, a2, -1, 0, \
0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000
test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0
0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000, FSR__
test_itof float.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__
test_itof float.s, f0, a2, 1, 1, \
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__
test_itof float.s, f0, a2, 1, 0, \
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__
test_itof float.s, f0, a2, 0x7fffffff, 0, \
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I
test_end
test ufloat_s
test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0
test_itof ufloat.s, f0, a2, 0, 0, 0, 0, 0, 0, FSR__
test_itof ufloat.s, f0, a2, 1, 1, \
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000
0x3f000000, 0x3f000000, 0x3f000000, 0x3f000000, FSR__
test_itof ufloat.s, f0, a2, 1, 0, \
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, FSR__
test_itof ufloat.s, f0, a2, 0x7fffffff, 0, \
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff
0x4f000000, 0x4effffff, 0x4f000000, 0x4effffff, FSR_I
test_itof ufloat.s, f0, a2, 0xffffffff, 0, \
0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff
0x4f800000, 0x4f7fffff, 0x4f800000, 0x4f7fffff, FSR_I
test_end
#endif

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#include "macros.inc"
#include "fpu.h"
test_suite fp0_div
#if XCHAL_HAVE_FP_DIV
.macro divs_seq q, a, b, r, y, y0, an, bn, e, ex
div0.s \y0, \b
nexp01.s \bn, \b
const.s \e, 1
maddn.s \e, \bn, \y0
mov.s \y, \y0
mov.s \ex, \b
nexp01.s \an, \a
maddn.s \y, \e, \y0
const.s \e, 1
const.s \q, 0
neg.s \r, \an
maddn.s \e, \bn, \y
maddn.s \q, \r, \y0
mkdadj.s \ex, \a
maddn.s \y, \e, \y
maddn.s \r, \bn, \q
const.s \e, 1
maddn.s \e, \bn, \y
maddn.s \q, \r, \y
neg.s \r, \an
maddn.s \y, \e, \y
maddn.s \r, \bn, \q
addexpm.s \q, \ex
addexp.s \y, \ex
divn.s \q, \r, \y
.endm
.macro div_s fr0, fr1, fr2
divs_seq \fr0, \fr1, \fr2, f9, f10, f11, f12, f13, f14, f15
.endm
.macro movfp fr, v
movi a2, \v
wfr \fr, a2
.endm
.macro check_res fr, r, sr
rfr a2, \fr
dump a2
movi a3, \r
assert eq, a2, a3
rur a2, fsr
movi a3, \sr
assert eq, a2, a3
.endm
test div_s
movi a2, 1
wsr a2, cpenable
test_op2 div_s, f0, f1, f2, 0x40000000, 0x40400000, \
0x3f2aaaab, 0x3f2aaaaa, 0x3f2aaaab, 0x3f2aaaaa, \
FSR_I, FSR_I, FSR_I, FSR_I
test_op2 div_s, f3, f4, f5, F32_1, F32_0, \
F32_PINF, F32_PINF, F32_PINF, F32_PINF, \
FSR_Z, FSR_Z, FSR_Z, FSR_Z
test_op2 div_s, f6, f7, f8, F32_0, F32_0, \
F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
FSR_V, FSR_V, FSR_V, FSR_V
/* MAX_FLOAT / 0.5 = +inf/MAX_FLOAT */
test_op2 div_s, f0, f1, f2, F32_MAX, F32_0_5, \
F32_PINF, F32_MAX, F32_PINF, F32_MAX, \
FSR_OI, FSR_OI, FSR_OI, FSR_OI
/* 0.5 / MAX_FLOAT = denorm */
test_op2 div_s, f0, f1, f2, F32_0_5, F32_MAX, \
0x00100000, 0x00100000, 0x00100001, 0x00100000, \
FSR_UI, FSR_UI, FSR_UI, FSR_UI
test_end
#endif
test_suite_end

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#include "macros.inc"
#include "fpu.h"
test_suite fp0_sqrt
#if XCHAL_HAVE_FP_SQRT
.macro sqrt_seq r, a, y, t1, hn, h2, t5, h
sqrt0.s \y, \a
const.s \t1, 0
maddn.s \t1, \y, \y
nexp01.s \hn, \a
const.s \r, 3
addexp.s \hn, \r
maddn.s \r, \t1, \hn
nexp01.s \t1, \a
neg.s \h2, \t1
maddn.s \y, \r, \y
const.s \r, 0
const.s \t5, 0
const.s \h, 0
maddn.s \r, \h2, \y
maddn.s \t5, \y, \hn
const.s \hn, 3
maddn.s \h, \hn, \y
maddn.s \t1, \r, \r
maddn.s \hn, \t5, \y
neg.s \y, \h
maddn.s \r, \t1, \y
maddn.s \h, \hn, \h
mksadj.s \y, \a
nexp01.s \a, \a
maddn.s \a, \r, \r
neg.s \t1, \h
addexpm.s \r, \y
addexp.s \t1, \y
divn.s \r, \a, \t1
.endm
.macro sqrt_s fr0, fr1
sqrt_seq \fr0, \fr1, f10, f11, f12, f13, f14, f15
.endm
.macro movfp fr, v
movi a2, \v
wfr \fr, a2
.endm
.macro check_res fr, r, sr
rfr a2, \fr
dump a2
movi a3, \r
assert eq, a2, a3
rur a2, fsr
movi a3, \sr
assert eq, a2, a3
.endm
test sqrt_s
movi a2, 1
wsr a2, cpenable
test_op1 sqrt_s, f0, f1, 0x40000000, \
0x3fb504f3, 0x3fb504f3, 0x3fb504f4, 0x3fb504f3, \
FSR_I, FSR_I, FSR_I, FSR_I
test_op1 sqrt_s, f3, f4, F32_1, \
F32_1, F32_1, F32_1, F32_1, \
FSR__, FSR__, FSR__, FSR__
test_op1 sqrt_s, f6, f7, F32_MINUS | F32_1, \
F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
FSR_V, FSR_V, FSR_V, FSR_V
test_end
#endif
test_suite_end

62
tests/tcg/xtensa/test_fp1.S
View File

@ -1,4 +1,5 @@
#include "macros.inc"
#include "fpu.h"
test_suite fp1
@ -9,7 +10,7 @@ test_suite fp1
wfr \fr, a2
.endm
.macro test_ord_ex op, br, fr0, fr1, v0, v1, r
.macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
@ -20,65 +21,70 @@ test_suite fp1
movt a2, a3, \br
assert eqi, a2, \r
rur a2, fsr
#if DFPU
movi a3, \sr
assert eq, a2, a3
#else
assert eqi, a2, 0
#endif
.endm
.macro test_ord op, br, fr0, fr1, v0, v1, r
.macro test_ord op, br, fr0, fr1, v0, v1, r, sr
movi a2, 0
wur a2, fcr
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
movi a2, 0x7c
wur a2, fcr
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
.endm
.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI
test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa
test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab
test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba
test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI
test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa
test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN
test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN
test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN
test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN
test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na
test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na
test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na
test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na
test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II
test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN
test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI
.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr
test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */
test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab, FSR__ /* ord < ord */
test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba, FSR__ /* ord > ord */
test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI, FSR__ /* ord +INF */
test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa, FSR__ /* +INF ord */
test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN, \qnan_sr /* ord -QNaN */
test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN, FSR_V /* ord -SNaN */
test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN, FSR_V /* ord +SNaN */
test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN, \qnan_sr /* ord +QNaN */
test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na, \qnan_sr /* -QNaN ord */
test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na, FSR_V /* -SNaN ord */
test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na, FSR_V /* +SNaN ord */
test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na, \qnan_sr /* +QNaN ord */
test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II, FSR__ /* +INF +INF */
test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN, \qnan_sr /* +INF +QNaN */
test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI, \qnan_sr /* +QNaN +INF */
.endm
test un_s
movi a2, 1
wsr a2, cpenable
test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1
test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, FSR__
test_end
test oeq_s
test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0
test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, FSR__
test_end
test ueq_s
test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1
test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, FSR__
test_end
test olt_s
test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0
test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, FSR_V
test_end
test ult_s
test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1
test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, FSR__
test_end
test ole_s
test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0
test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, FSR_V
test_end
test ule_s
test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1
test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, FSR__
test_end
.macro test_cond op, fr0, fr1, cr, v0, v1, r

170
tests/tcg/xtensa/test_lsc.S
View File

@ -1,4 +1,5 @@
#include "macros.inc"
#include "fpu.h"
test_suite lsc
@ -9,9 +10,14 @@ test lsi
wsr a2, cpenable
movi a2, 1f
lsi f0, a2, 0
lsi f1, a2, 4
#if DFPU
lsi f2, a2, 8
lsip f0, a2, 8
#else
lsi f0, a2, 0
lsiu f2, a2, 8
#endif
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f0
@ -34,13 +40,18 @@ test ssi
movi a2, 1f
movi a3, 0x40800000
wfr f3, a3
ssi f3, a2, 0
movi a3, 0x40a00000
wfr f4, a3
ssi f4, a2, 4
movi a3, 0x40c00000
wfr f5, a3
ssi f4, a2, 4
#if DFPU
ssi f5, a2, 8
ssip f3, a2, 8
#else
ssi f3, a2, 0
ssiu f5, a2, 8
#endif
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
@ -62,11 +73,16 @@ test_end
test lsx
movi a2, 1f
movi a3, 0
movi a4, 4
movi a5, 8
lsx f7, a2, a4
#if DFPU
lsx f8, a2, a5
lsxp f6, a2, a5
#else
lsx f6, a2, a3
movi a3, 4
lsx f7, a2, a3
movi a3, 8
lsxu f8, a2, a3
lsxu f8, a2, a5
#endif
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f6
@ -87,18 +103,23 @@ test_end
test ssx
movi a2, 1f
movi a3, 0
movi a4, 0x41200000
wfr f9, a4
ssx f9, a2, a3
movi a3, 4
movi a4, 0x41300000
wfr f10, a4
ssx f10, a2, a3
movi a3, 8
movi a4, 0x41400000
wfr f11, a4
ssxu f11, a2, a3
movi a3, 0
movi a4, 4
movi a5, 8
ssx f10, a2, a4
#if DFPU
ssx f11, a2, a5
ssxp f9, a2, a5
#else
ssx f9, a2, a3
ssxu f11, a2, a5
#endif
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
@ -119,4 +140,127 @@ test_end
#endif
#if XCHAL_HAVE_DFP
#if XCHAL_HAVE_BE
#define F64_HIGH_OFF 0
#else
#define F64_HIGH_OFF 4
#endif
.macro movdf fr, hi, lo
movi a2, \hi
movi a3, \lo
wfrd \fr, a2, a3
.endm
test ldi
movi a2, 1
wsr a2, cpenable
movi a2, 1f
ldi f1, a2, 8
ldi f2, a2, 16
ldip f0, a2, 16
movi a3, 1f + 16
assert eq, a2, a3
rfrd a2, f0
movi a3, 0x3ff00000
assert eq, a2, a3
rfrd a2, f1
movi a3, 0x40000000
assert eq, a2, a3
rfrd a2, f2
movi a3, 0x40080000
assert eq, a2, a3
.data
.align 8
1:
.double 1, 2, 3
.text
test_end
test sdi
movdf f3, 0x40800000, 0
movdf f4, 0x40a00000, 0
movdf f5, 0x40c00000, 0
movi a2, 1f
sdi f4, a2, 8
sdi f5, a2, 16
sdip f3, a2, 16
movi a3, 1f + 16
assert eq, a2, a3
l32i a4, a2, -16 + F64_HIGH_OFF
movi a3, 0x40800000
assert eq, a4, a3
l32i a4, a2, -8 + F64_HIGH_OFF
movi a3, 0x40a00000
assert eq, a4, a3
l32i a4, a2, F64_HIGH_OFF
movi a3, 0x40c00000
assert eq, a4, a3
.data
.align 8
1:
.double 0, 0, 0
.text
test_end
test ldx
movi a2, 1f
movi a3, 0
movi a4, 8
movi a5, 16
ldx f7, a2, a4
ldx f8, a2, a5
ldxp f6, a2, a5
movi a3, 1f + 16
assert eq, a2, a3
rfrd a2, f6
movi a3, 0x401c0000
assert eq, a2, a3
rfrd a2, f7
movi a3, 0x40200000
assert eq, a2, a3
rfrd a2, f8
movi a3, 0x40220000
assert eq, a2, a3
.data
.align 8
1:
.double 7, 8, 9
.text
test_end
test sdx
movdf f9, 0x41200000, 0
movdf f10, 0x41300000, 0
movdf f11, 0x41400000, 0
movi a2, 1f
movi a3, 0
movi a4, 8
movi a5, 16
sdx f10, a2, a4
sdx f11, a2, a5
sdxp f9, a2, a5
movi a3, 1f + 16
assert eq, a2, a3
l32i a4, a2, -16 + F64_HIGH_OFF
movi a3, 0x41200000
assert eq, a4, a3
l32i a4, a2, -8 + F64_HIGH_OFF
movi a3, 0x41300000
assert eq, a4, a3
l32i a4, a2, F64_HIGH_OFF
movi a3, 0x41400000
assert eq, a4, a3
.data
.align 8
1:
.double 0, 0, 0
.text
test_end
#endif
test_suite_end