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hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board 

Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.

If machine USB support is not enabled, create unimplemented devices
for the USB memory ranges to avoid crashes when booting Linux.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240115182757.1095012-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Guenter Roeck 2024-01-15 10:27:55 -08:00 committed by Peter Maydell
parent b8e2d3f86c
commit 43eef24f52
4 changed files with 57 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/system/arm/bananapi_m2u.rst
View File

@ -23,6 +23,7 @@ The Banana Pi M2U machine supports the following devices:
* GMAC ethernet
* Clock Control Unit
* TWI (I2C)
* USB 2.0
Limitations
"""""""""""
@ -33,7 +34,6 @@ Currently, Banana Pi M2U does *not* support the following features:
- Audio output
- Hardware Watchdog
- Real Time Clock
- USB 2.0 interfaces
Also see the 'unimplemented' array in the Allwinner R40 SoC module
for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-r40.c``

2
hw/arm/Kconfig
View File

@ -415,6 +415,8 @@ config ALLWINNER_R40
select ARM_TIMER
select ARM_GIC
select UNIMP
select USB_OHCI
select USB_EHCI_SYSBUS
select SD
config RASPI

47
hw/arm/allwinner-r40.c
View File

@ -23,6 +23,7 @@
#include "qemu/bswap.h"
#include "qemu/module.h"
#include "qemu/units.h"
#include "hw/boards.h"
#include "hw/qdev-core.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
@ -45,6 +46,10 @@ const hwaddr allwinner_r40_memmap[] = {
[AW_R40_DEV_MMC1] = 0x01c10000,
[AW_R40_DEV_MMC2] = 0x01c11000,
[AW_R40_DEV_MMC3] = 0x01c12000,
[AW_R40_DEV_EHCI1] = 0x01c19000,
[AW_R40_DEV_OHCI1] = 0x01c19400,
[AW_R40_DEV_EHCI2] = 0x01c1c000,
[AW_R40_DEV_OHCI2] = 0x01c1c400,
[AW_R40_DEV_CCU] = 0x01c20000,
[AW_R40_DEV_PIT] = 0x01c20c00,
[AW_R40_DEV_UART0] = 0x01c28000,
@ -89,9 +94,9 @@ static struct AwR40Unimplemented r40_unimplemented[] = {
{ "crypto", 0x01c15000, 4 * KiB },
{ "spi2", 0x01c17000, 4 * KiB },
{ "sata", 0x01c18000, 4 * KiB },
{ "usb1-host", 0x01c19000, 4 * KiB },
{ "usb1-phy", 0x01c19800, 2 * KiB },
{ "sid", 0x01c1b000, 4 * KiB },
{ "usb2-host", 0x01c1c000, 4 * KiB },
{ "usb2-phy", 0x01c1c800, 2 * KiB },
{ "cs1", 0x01c1d000, 4 * KiB },
{ "spi3", 0x01c1f000, 4 * KiB },
{ "rtc", 0x01c20400, 1 * KiB },
@ -181,6 +186,10 @@ enum {
AW_R40_GIC_SPI_MMC2 = 34,
AW_R40_GIC_SPI_MMC3 = 35,
AW_R40_GIC_SPI_EMAC = 55,
AW_R40_GIC_SPI_OHCI1 = 64,
AW_R40_GIC_SPI_OHCI2 = 65,
AW_R40_GIC_SPI_EHCI1 = 76,
AW_R40_GIC_SPI_EHCI2 = 78,
AW_R40_GIC_SPI_GMAC = 85,
};
@ -276,6 +285,13 @@ static void allwinner_r40_init(Object *obj)
TYPE_AW_SDHOST_SUN50I_A64);
}
for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
object_initialize_child(obj, "ohci[*]", &s->ohci[i],
TYPE_SYSBUS_OHCI);
}
object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
@ -407,6 +423,33 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
/* USB */
for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true,
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2
: AW_R40_DEV_EHCI1]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
qdev_get_gpio_in(DEVICE(&s->gic),
i ? AW_R40_GIC_SPI_EHCI2
: AW_R40_GIC_SPI_EHCI1));
object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2
: AW_R40_DEV_OHCI1]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
qdev_get_gpio_in(DEVICE(&s->gic),
i ? AW_R40_GIC_SPI_OHCI2
: AW_R40_GIC_SPI_OHCI1));
}
/* SD/MMC */
for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),

9
include/hw/arm/allwinner-r40.h
View File

@ -30,6 +30,8 @@
#include "hw/i2c/allwinner-i2c.h"
#include "hw/net/allwinner_emac.h"
#include "hw/net/allwinner-sun8i-emac.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@ -44,6 +46,10 @@ enum {
AW_R40_DEV_MMC1,
AW_R40_DEV_MMC2,
AW_R40_DEV_MMC3,
AW_R40_DEV_EHCI1,
AW_R40_DEV_OHCI1,
AW_R40_DEV_EHCI2,
AW_R40_DEV_OHCI2,
AW_R40_DEV_CCU,
AW_R40_DEV_PIT,
AW_R40_DEV_UART0,
@ -88,6 +94,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
* which are currently emulated by the R40 SoC code.
*/
#define AW_R40_NUM_MMCS 4
#define AW_R40_NUM_USB 2
#define AW_R40_NUM_UARTS 8
struct AwR40State {
@ -106,6 +113,8 @@ struct AwR40State {
AwSRAMCState sramc;
AwA10PITState timer;
AwSdHostState mmc[AW_R40_NUM_MMCS];
EHCISysBusState ehci[AW_R40_NUM_USB];
OHCISysBusState ohci[AW_R40_NUM_USB];
AwR40ClockCtlState ccu;
AwR40DramCtlState dramc;
AWI2CState i2c0;