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target/arm: Update aa64_zva_access for EL2
The comment that we don't support EL2 is somewhat out of date. Update to include checks against HCR_EL2.TDZ. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -4159,11 +4159,27 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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/* We don't implement EL2, so the only control on DC ZVA is the
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* bit in the SCTLR which can prohibit access for EL0.
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*/
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if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
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return CP_ACCESS_TRAP;
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int cur_el = arm_current_el(env);
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if (cur_el < 2) {
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uint64_t hcr = arm_hcr_el2_eff(env);
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if (cur_el == 0) {
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
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return CP_ACCESS_TRAP_EL2;
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}
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} else {
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if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
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return CP_ACCESS_TRAP;
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}
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if (hcr & HCR_TDZ) {
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return CP_ACCESS_TRAP_EL2;
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}
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}
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} else if (hcr & HCR_TDZ) {
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return CP_ACCESS_TRAP_EL2;
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}
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}
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return CP_ACCESS_OK;
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}
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