From 433efb4cca1d942b6849be953ea166b492e9bb59 Mon Sep 17 00:00:00 2001
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Date: Wed, 28 Aug 2019 18:26:41 +0200
Subject: [PATCH] target/mips: Clean up handling of CP0 register 16
Clean up handling of CP0 register 16.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-18-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 3 ++-
target/mips/translate.c | 60 ++++++++++++++++++++---------------------
2 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 8ecfdb302a..d6405ad241 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -375,7 +375,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG16__CONFIG3 3
#define CP0_REG16__CONFIG4 4
#define CP0_REG16__CONFIG5 5
-#define CP0_REG00__CONFIG7 7
+#define CP0_REG16__CONFIG6 6
+#define CP0_REG16__CONFIG7 7
/* CP0 Register 17 */
#define CP0_REG17__LLADDR 0
#define CP0_REG17__MAAR 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 238066fe93..48086409f1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7246,36 +7246,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -7971,45 +7971,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_helper_mtc0_config4(cpu_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
/* ignored */
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
/* ignored */
register_name = "Config7";
break;
@@ -8718,36 +8718,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -9434,33 +9434,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
/* currently ignored */
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */