mirror of https://github.com/xemu-project/xemu.git
target/arm: Allow users to set the number of VFP registers
Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support have 16 64-bit FPU registers and not 32 registers. Let users set the number of VFP registers with a CPU property. The primary use case of this property is for the Cortex A7 of the Aspeed AST2600 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -316,6 +316,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
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&error_abort);
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object_property_set_link(OBJECT(&s->cpu[i]), "memory",
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OBJECT(s->memory), &error_abort);
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@ -1277,6 +1277,9 @@ static Property arm_cpu_cfgend_property =
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static Property arm_cpu_has_vfp_property =
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DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
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static Property arm_cpu_has_vfp_d32_property =
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DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
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static Property arm_cpu_has_neon_property =
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DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
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@ -1408,6 +1411,22 @@ void arm_cpu_post_init(Object *obj)
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}
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}
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if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) {
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cpu->has_vfp_d32 = true;
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if (!kvm_enabled()) {
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/*
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* The permitted values of the SIMDReg bits [3:0] on
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* Armv8-A are either 0b0000 and 0b0010. On such CPUs,
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* make sure that has_vfp_d32 can not be set to false.
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*/
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if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) &&
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!arm_feature(&cpu->env, ARM_FEATURE_M))) {
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qdev_property_add_static(DEVICE(obj),
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&arm_cpu_has_vfp_d32_property);
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}
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}
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
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cpu->has_neon = true;
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if (!kvm_enabled()) {
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@ -1674,6 +1693,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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return;
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}
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if (cpu->has_vfp_d32 != cpu->has_neon) {
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error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
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return;
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}
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if (!cpu->has_vfp_d32) {
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uint32_t u;
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u = cpu->isar.mvfr0;
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u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
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cpu->isar.mvfr0 = u;
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}
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if (!cpu->has_vfp) {
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uint64_t t;
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uint32_t u;
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@ -924,6 +924,8 @@ struct ArchCPU {
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bool has_pmu;
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/* CPU has VFP */
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bool has_vfp;
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/* CPU has 32 VFP registers */
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bool has_vfp_d32;
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/* CPU has Neon */
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bool has_neon;
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/* CPU has M-profile DSP extension */
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